ppc440grx Applied Micro Circuits Corporation (AMCC), ppc440grx Datasheet - Page 85

• Manufacturer Part Number: ppc440grx
• Description: Powerpc 440grx Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

Revision 1.11 – July 22, 2008
Table 25. I/O Timing—DDR SDRAM T
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 166MHz.
Table 26. I/O Timing—DDR SDRAM T
Notes:
1. Clock speed is 166MHz. T
2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs,
3. To obtain adjusted T
4. To obtain adjusted T
AMCC Proprietary
Preliminary Data Sheet
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
MemAddr00:13
BA0:2
BankSel0:1
ClkEn
CAS
RAS
WE
edge.
use the following values by subtracting them from T
18 loads adjust by 2.12ns
T
T
9 loads adjust by 1.12ns
5 loads adjust by 0.41ns
SK
SK
maximum (0.5T
minimum (0.5T
Signal Name
Signal Name
CYC
SA
CYC
HA
values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract
values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add
+ T
− T
SK
SK
SK
is referenced to MemClkOut falling edge. T
min).
max).
DS
SK
, T
SA
Minimum
−0.960
, and T
SA
and adding them to T
Minimum
HA
T
−0.030
−0.030
−0.050
−0.110
−0.140
−0.120
−0.060
−0.010
−0.140
SK
440GRx – PPC440GRx Embedded Processor
(ns)
Maximum
−0.270
SA
and T
SK
T
DS
and T
HA
(ns)
are referenced to MemClkOut rising
HA
Minimum
:
T
SA
3.27
(ns)
Maximum
+0.650
+0.620
+0.580
+0.480
+0.410
+0.480
+0.580
+0.690
+0.420
Minimum
T
HA
2.04
(ns)
85