npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 51

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npe405h

Manufacturer Part Number
npe405h
Description
Powernp Npe405h Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
NPe405H – PowerNP NPe405H Embedded Processor
Table 6. Signal Functional Description (Sheet 9 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
AMCC Proprietary
System Interface
Trace Interface
Power Pins
Other Pins
GPIO0_00:31
GPIO1_00:31
Signal Name
SysReset
Reserved
[TrcClk]
TmrClk
[TS3:6]
SysClk
TestEn
[TS1E]
[TS2E]
[TS1O]
[TS2O]
SysErr
OV
AV
GND
Halt
V
DD
DD
DD
Main System Clock input.
Main System Reset.
Set to 1 when a Machine Check is generated.
Halt from external debugger.
System General Purpose I/O.
Communications General Purpose I/O.
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
This input must toggle at a rate of less than one half the CPU
core frequency (less than 100MHz in most cases). In most
cases this input toggles much slower (in the 1MHz to 10MHz
range).
Even Trace execution status.To access this function, software
must toggle a DCR bit.
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
Trace Status. To access this function, software must toggle a
DCR bit.
Trace interface clock. A toggling signal that is always half of
the CPU core frequency. To access this function, software
must toggle a DCR bit.
Ground
Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, and
P09-P14 are also thermal balls.
Logic voltage—2.5V
Output driver voltage—3.3V
Filtered PLL voltage—2.5V
Do not connect signals, voltage, or ground to these pins.
Description
Revision 1.02 – November 16, 2007
I/O
I/O
I/O
I/O
n/a
O
O
O
O
O
I
I
I
I
I
I
I
I
3.3V Analog
Wire w/ESD
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Wire w/ESD
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Rcvr w/PD
Hardwire
Hardwire
Hardwire
3.3V DC
Type
Data Sheet
n/a
DS2011
Notes
1, 2
1
1
1
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