npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 67

• Manufacturer Part Number: npe405h
• Description: Powernp Npe405h Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

NPe405H – PowerNP NPe405H Embedded Processor
Table 16. I/O Specifications—266MHz (Sheet 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
AMCC Proprietary
SDRAM Interface
BA1:0
BankSel3:0
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:00
MemData00:31
RAS
WE
External Slave Peripheral Bus Interface
[DMAReq0:3]
[DMAAck0:3]
[EOT0:3/TC0:3]
PerAddr04:31
PerBLast
PerCS0
[PerCS1:7]
PerData00:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
PerClk
PerErr
External Master Peripheral Bus Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
IIC EEPROM Controller
IECSCL
IECSDA
command is used by SDRAM. Output times in table are in cycle 1.
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
Signal
Setup Time
(T IS min)
async
async
[3.8]
[3.5]
n/a
n/a
n/a
n/a
n/a
n/a
1.6
n/a
1.6
n/a
n/a
n/a
2.4
3.0
n/a
n/a
4.4
n/a
2.7
3.5
5.8
2.4
n/a
2.3
n/a
n/a
3.5
n/a
n/a
2.3
3.2
Input (ns)
Hold Time
(T IH min)
async
async
[0.0]
[0.0]
n/a
n/a
n/a
n/a
n/a
n/a
1.0
n/a
1.0
n/a
n/a
n/a
0.0
0.0
n/a
n/a
1.0
n/a
0.0
0.0
0.0
0.0
n/a
0.0
n/a
n/a
0.0
n/a
n/a
0.0
0.0
Valid Delay
(T OV max)
async
async
[6.1]
[6.4]
[7.1]
6.0
4.7
5.7
4.2
4.7
4.7
4.8
6.0
4.8
5.7
6.2
n/a
6.6
5.3
5.3
7.2
7.5
6.9
5.6
n/a
5.7
0.0
n/a
5.0
5.1
n/a
8.0
5.4
n/a
n/a
Output (ns)
Hold Time
(T OH min)
async
async
[1.0]
[1.0]
[1.0]
1.8
1.2
1.7
1.2
1.2
1.2
1.2
1.7
1.2
1.6
2.2
n/a
1.0
1.2
1.2
1.2
1.3
1.1
1.2
n/a
1.3
0.7
n/a
1.2
1.2
n/a
0.0
1.4
n/a
n/a
(maximum)
Output Current (mA)
I/O H
n/a
n/a
n/a
n/a
n/a
n/a
19
19
19
40
19
19
19
19
19
19
19
12
12
17
12
12
12
17
12
17
12
12
17
12
12
19
12
17
17
Revision 1.02 – November 16, 2007
(minimum)
I/O L
n/a
n/a
n/a
n/a
n/a
n/a
12
12
12
25
12
12
12
12
12
12
12
11
11
11
11
12
11
11
8
8
8
8
8
8
8
8
8
8
8
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
Data Sheet
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
Clock
DS2011
Notes
2, 3
2, 3
2, 3
2, 3
2, 3
3
3
3
3
3
3
5
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