hx6136 Honeywell International's Solid State Electronics Center (SSEC), hx6136 Datasheet - Page 7

• Manufacturer Part Number: hx6136
• Description: First-in First-out Memory
• Manufacturer: Honeywell International's Solid State Electronics Center (SSEC)

FIFO – HX6409/HX6218/HX6136
AC TIMING CHARACTERISTICS (1)
www.honeywell.com/radhard
Symbol
TCKW
TCKR
TCKH
TCKH
TCKL
TA
TOH
TFH
TSD
THD
TSEN
THEN
TOE
TOLZ
TOHZ
TFD
TSKEW1
TSKEW2
TPMR
TSCMR
TOHMR
TMRR
TMRF
TAMR
TSMRP
THMRP
TAP
TOHP
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and
(2) Worst case operating conditions: VDD=4.5V to 5.5V, TC=-55°C to +125°C, post total dose at 25°C.
(3) For flag updates tskew1 is the minimum time an opposite clock can occur after a clock and still not be included
(4) For flag updates, tskew2 is the minimum time an opposite clock can occur before a clock and still be included in
(5) Timing parameters are defined in Figures 1 through 6
(6) This parameter is tested during design characterization only.
fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing characteristics Table,
capacitive output loading C
in the current clock cycle. At less than tskew1, inclusion of the opposite clock is arbitrary.
the current clock cycle. At less than tskew2, inclusion of the opposite clock is arbitrary.
Test Parameter
Previous Output Data Hold After Rd High
Previous Flag Hold After Rd/Wr High
Data Hold
Enable Hold
OE Low to Output Data in Low Z
OE High to Output Data in High Z
Flag Delay
Opposite Clock after Clock (3)
Opposite Clock before Clock (4)
Last Valid Clock Low Set-up to Master Reset Low
Data Hold from Master Reset Low
Parity Program Mode – Data Hold Time from MR High
Write Clock Cycle (6)
Read Clock Cycle
Clock High Read
Clock High Write
Clock Low
Data Access Time
Data Set-UP
Enable Set-UP
OE Low to Output Data Valid
Master Reset Pulse Width (Low)
Master Reset Recovery
Master Reset High to Flags Valid
Master Reset High to Data Outputs Low
Parity Program Mode – MR low Set-up to CKW High
Parity Program Mode – MR High Hold from CKW High
Parity Program Mode – Data Access Time
L
=50pF. For C
L
>50pF, derate access times by 0.02 ns/pF (typical).
-55°C to 125°C
Worst Case
Min
24
36
26
14
10
12
25
25
10
2
2
4
8
2
1
0
0
2
8
4
2
-
-
-
-
-
-
-
Max
30
10
10
17
17
17
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(2)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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