hdd16m72d9w ETC-unknow, hdd16m72d9w Datasheet - Page 4

• Manufacturer Part Number: hdd16m72d9w
• Description: Sdram Module 128mbyte 16mx72bit , Based 16mx8, 4banks Ref., 184pin-dimm With Unbuffered
• Manufacturer: ETC-unknow

HANBit
PIN FUNCTION DESCRIPTION
CK, /CK
CKE
/CS
A0 ~ A11
BA0 ~ BA1
/RAS
/CAS
/WE
DQS0 ~ 7
DM0~7
DQ0 ~ 63
WP
VDDQ
VDD
VSS
VREF
URL : www.hbe.co.kr
REV 1.0 (November.2002)
Pin
Clock
Clock Enable
Chip Select
Address
Bank select address
Row address strobe
Columnaddress strobe
Write enable
Data Strobe
Input Data Mask
Data input/output
Write Protection
Supply
Supply
Supply
Supply
Name
CK and /CK are differential clock inputs. All address and control input signals are
sampled on the positive edge of CK and negative edge of CK. Output (read) data
is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides
PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
except for disabling outputs, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE are disabled during power-down and self refresh
modes, providing low standby power. CKE will recognizean LVCMOS LOW level
prior to VREF being stable on power-up.
/CS enables(registered LOW) and disables(registered HIGH) the command
decoder.
All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the
command code.
Addresses are multiplexed on the same pins. Address : A0 ~ A11
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
command is being applied.
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. DM pins include dummy loading internally, to matches the
DQ and DQS load-ing.
Data inputs/outputs are multiplexed on the same pins.
WP pin is connected to Vcc.
When WP is “high” , EEPROM Programming will be inhibited and the entire
memory will be write-protected.
DQ Power Supply : +2.5V ± 0.2V.
Power Supply : +2.5V ± 0.2V (device specific).
DQ Ground.
SSTL_2 reference voltage.
4
Input Function
HDD16M72D9W
HANBit Electronics Co.,Ltd.