hdd16m72d9w ETC-unknow, hdd16m72d9w Datasheet - Page 8

• Manufacturer Part Number: hdd16m72d9w
• Description: Sdram Module 128mbyte 16mx72bit , Based 16mx8, 4banks Ref., 184pin-dimm With Unbuffered
• Manufacturer: ETC-unknow

HANBit
Notes :
URL : www.hbe.co.kr
REV 1.0 (November.2002)
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1.
2.
3.
4.
5.
6.
7.
8.
9.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. t
This derating table is used to increase t
based on the lesser of AC-AC slew rate and DC-DC slew rate.
This derating table is used to increase t
on the lesser of AC-AC slew rate and DC-DC slew rate.
This derating table is used to increase t
This derating table is used to increase t
calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-
0/5ns/V. Input S/H slew rate based on larger of AC -AC delta rise/fall rate and DC-DC delta rise/fall rate.
Maximum burst refresh cycle : 8
The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z
to logic Low) applies when no writes were previously in progress on the bus. If a pre vious write was in progress, DQS could be
High at this time, depending on t
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
A write command can be applied with t
For registered DIMMs, t
jitter due to crosstalk (t
Input Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Plateau Derating
I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Input Setup/Hold Slew Rate
Input Setup/Hold Slew Rate
Delta Rise/Fall Rate
I/O Input Level
(V/ns)
(V/ns)
(ns/V)
±0.25
(mV)
±0.5
0.5
0.4
0.3
0.5
0.4
0.3
280
0
JIT
CL
(crosstalk) ) on the DIMM.
and t
CH
DQSS
are
DS
DS
DS
DS
.
/t
/t
/t
/t
RCD
DH
DH
DH
DH
+100
+150
Δ t
Δ t
+100
45% of the period including both the half period jitter ( t
Δ t
Δ t
(ps)
+50
(ps)
+75
(ps)
+50
(ps)
+50
0
0
0
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based
in the case where the input level is flat below V
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is
satisfied after this command.
DS
DS
IS
IS
8
+100
+150
Δ t
Δ t
+100
Δ t
Δ t
(ps)
+50
(ps)
+75
(ps)
+50
(ps)
+50
0
0
0
DH
DH
IH
IH
CK
is actual to the system clock cycle time.
REF
HDD16M72D9W
JIT
310mV for a duration of up to 2ns.
(HP) ) of the PLL and the half
HANBit Electronics Co.,Ltd.