km29w32000ts Samsung Semiconductor, Inc., km29w32000ts Datasheet - Page 18

• Manufacturer Part Number: km29w32000ts
• Description: 8-bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10 s(t
of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE
with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last
column address(column 511 or 527 depending on state of SE pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential read.
Waiting 10 s again allows for reading of the selected page. The sequential read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Addresses A
of the spare area while addresses A
mented for sequential read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00H/01H) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each
read operation.
KM29W32000TS
Figure 3. Read1 Operation
CLE
CE
WE
ALE
R/B
RE
I/O
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00H) at next cycle.
0
~
7
00H
01H
A
0
Start Add.(3Cycle)
~ A
7
& A
4
to A
9
~ A
7
21
are ignored. Unless the operation is aborted, the page address is automatically incre-
R
). The CPU can detect the completion of this data transfer(t
1st half array
t
R
(00H Command)
Data Field
2nd half array
18
Spare Field
1st half array
Data Output(Sequential)
FLASH MEMORY
(01H Command)*
Data Field
0
to A
2nd half array
R
3
) by analyzing the output
set the starting address
Spare Field