tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 20

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper
2.17 Test Pattern Generator
The test pattern generator and monitor (TPG and TPM) is a set of configurable test pattern generators and moni-
tors for local self-test, maintenance, and troubleshooting operations.
The TPG feeds one or more T1/E1/DS2 test signals (via data, clock, and FS or AIS signal paths) to the crosspoint
switch which can redistribute or broadcast these signals to any valid channel in the framer, external I/O, M13 map-
per, or VT mapper blocks. The TPG can also generate DS3 test signals.
Any channel arriving at the cross connect may be routed to the test monitor. The test monitors can automatically
detect/count bit errors in a pseudorandom test sequence, loss of frame, or loss of synchronization. The TPM can
provide an interrupt to the control system or it can be operated in a polled mode.
Simultaneous testing of DS1, E1, DS2, and DS3 signals is supported (one channel each).
Supported test patterns are: pseudorandom bit sequence (PRBS15, PRBS20), alternating zeros/ones, and an all-
ones pattern.
The test pattern can be transmitted either unframed or as the payload of a framed signal, as defined in ITU-T Rec-
ommendation O.150.
Single bit-errors may be injected into any test pattern, under register control.
2.18 28-Channel Framer
The block diagrams of the 84 T1/63E1-channel framer in the switching application in the CHI, parallel system bus,
and CHI with byte-synchronous VT mapping, are shown in Figure 10, Figure 11, and Figure 12 (only the major
functional blocks are shown). The block diagrams of the 84 T1/63E1-channel framers in the transport application
are shown in Figure 13 and Figure 14 (only the major functional blocks are shown).
Figure 10. Ultramapper Switching Mode for Framer in Concentration Highway Interface (CHI) Configuration
20
20
INTERFACE
INTERFACE
TRANSMIT
RECEIVE
SYSTEM
SYSTEM
ULTRAMAPPER: FRAMER
(EXTRACTION)
PROCESSOR
SIGNALING
PROCESSOR
(INSERTION)
SIGNAL
(continued)
RECEIVE
HDLC
PERFORMANCE
TRANSMIT
MONITOR
FACILITY DATA
HDLC
TRANSMIT
FACILITY DATA
RECEIVE
LINK
LINK
ESF PRM PATH
FORMATTER
TRANSMIT
RECEIVE
ALIGNER
FRAME
FRAME
CONNECT
MAPPER
FRAMER
CROSS
DS1
TO
Advance Data Sheet, Rev. 2
M12 MULTIPLEXER
ULTRAMAPPER
ULTRAMAPPER
VT MAPPER
INTERFACE
INTERFACE
Agere Systems Inc.
July 2001
5-8926.a (F)