FM24CL16_05 RAMTRON [Ramtron International Corporation], FM24CL16_05 Datasheet
FM24CL16_05
Related parts for FM24CL16_05
FM24CL16_05 Summary of contents
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FM24CL16 16Kb FRAM Se rial 3V Memory Features 16K bit Ferroelectric Nonvolatile RAM Organized as 2,048 x 8 bits Unlimited Read/Write Cycles 45 year Data Retention NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1MHz Maximum ...
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Counter ` SDA Serial to Parallel Converter SCL Control Logic WP Pin Description Pin Name Type Pin Description SDA I/O Serial Data Address: This is a bi-directional data pin for the two-wire interface. It employs an open-drain output and is ...
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Overview The FM24CL16 is a serial FRAM memory. The memory array is logically organized as a 2,048 x 8 memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. ...
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SCL SDA Stop (Master) (Master) Stop Condition A stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations using the FM24CL16 must end with a Stop condition. If ...
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Page Slave ID Select Figure 4. Slave Address Word Address After the FM24CL16 (as receiver) acknowledges the slave ID, the master will place the word address on the bus for a write operation. The ...
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Start By Master S Slave Address By FM24CL16 Start By Master S Slave Address By FM24CL16 Read Operation There are two types of read operations. They are current address read and selective address read current address read, the ...
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Start By Master S By FM24CL16 Start Address By Master S Slave Address By FM24CL16 Address Start By Master S Slave ...
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Electrical Specifications Absolute Maximum Ratings Symbol V Power Supply Voltage with respect Voltage on any pin with respect Storage Temperature STG T Lead temperature (Soldering, 10 seconds) LEAD V Electrostatic Discharge Voltage ...
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AC Parameters ( Symbol Parameter f SCL Clock Frequency SCL t Clock Low Period LOW t Clock High Period HIGH t SCL Low to SDA Data Out Valid AA t Bus ...
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Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are ...
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Mechanical Drawing 8-pin SOIC (JEDEC MS-012 variation AA) Pin 1 1.35 4.90 0.10 ± 1.75 1.27 0.33 0.51 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme Legend: XXXX= part number, P= ...
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TDFN (3.0mm x 6.4mm body, 0.65mm pitch) Pin 1 3.00 ±0.1 0.75 ±0.05 0.65 0.25 ±0.05 Note: All dimensions in millimeters. This package is footprint compatible with the 8-pin TSSOP. TDFN Package Marking Scheme for Body Size 3mm x ...
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Revision History Revision Date 1.0 2/15/01 1.1 9/29/01 2.0 2/22/02 2.1 3/24/03 2.2 6/24/04 3.0 7/14/04 3.1 11/19/04 3.2 3/8/05 3.3 11/28/05 Rev 3.3 Nov. 2005 Summary Initial Release. Endurance changed to unlimited. Changed to Production status. Added clarification to ...