FM24CL64B-GA RAMTRON [Ramtron International Corporation], FM24CL64B-GA Datasheet
FM24CL64B-GA
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FM24CL64B-GA Summary of contents
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... Pin Configuration A0 caused VSS higher than Pin Name A0-A2 SDA SCL WP VDD VSS Ordering Information FM24CL64B-G FM24CL64B-GATR 2 C) protocol. The VDD SCL 3 6 SDA 4 5 Function Device Select Address Serial Data/address Serial Clock Write Protect ...
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... When WP is connected to ground, all addresses may be written. This pin is pulled down internally. VDD Supply Supply Voltage VSS Supply Ground Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Address Latch Converter Control Logic Figure 1. FM24CL64B Block Diagram FRAM Array 8 Data Latch ...
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... This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24CL64B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example ...
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... Slave Address The first byte that the FM24CL64B expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the device type or slave ID, the device select address bits, a page address bit, and a bit that specifies if the transaction is a read or a write ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24CL64B can begin. For a read operation the FM24CL64B will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24CL64B will transfer the next sequential byte ...
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... Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Address & Data 0 A Address MSB A Address LSB Acknowledge Figure 5 ...
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... Address MSB By F-RAM Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) master issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a „1‟. The operation is now a current address read. ...
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... This parameter is characterized but not tested. 5. The input pull-down circuit is stronger (40K) when the input voltage is below V is above Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp (AEC-Q100-002 Rev. E) (AEC-Q100-011 Rev. B) (AEC-Q100-003 Rev. E) =3.0V to 3.6V unless otherwise specified) DD Min 3 ...
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... First Access (Start condition Last Access (Stop condition) to Power Down ( Rise Time Fall Time VF DD Notes 1. Slope measured at any point Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) =3.0V to 3.6V unless otherwise specified) DD Min Max Min 0 100 0 4.7 1.3 4.0 0.6 3 4.7 1.3 4.0 0.6 4.7 0 ...
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... Typical Grade 1 Operating Profile 1600 1400 1200 1000 800 600 400 200 100 105 110 115 120 125 Temperature (°C) Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp HIGH 1/fSCL t AA Stop Start ...
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... Legend: XXXXX= part number, P=package type R=rev code, LLLLLLL= lot code XXXXXX-P RIC=Ramtron Int‟l Corp, YY=year, WW=work week RLLLLLLL RICYYWW Example: FM24CL64B-GA, “Green” SOIC, Automotive Temperature, Rev A, Lot L3502G1, Year 2011, Work Week 04 24CL64BGA AL3502G1 RIC1104 Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp ...
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... Revision History Revision Date 1.0 2/22/2011 1.1 6/2/2011 Rev. 1.1 June 2011 FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Summary Initial Release Added ESD ratings. Fixed notes 4 and table. Page ...