DS023 Xilinx Corp., DS023 Datasheet

DS023

Manufacturer Part Number

DS023

Description

Xcr3032xl 32 Macrocell CPLD

Manufacturer

Xilinx Corp.

Datasheet

1.DS023.pdf (8 pages)

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DS023 (v1.6) June 27, 2002

Features

•

Table 1: I

DS023 (v1.6) June 27, 2002

Preliminary Product Specification

Lowest power 32 macrocell CPLD

5.0 ns pin-to-pin logic delays

System frequencies up to 200 MHz

32 macrocells with 750 usable gates

Available in small footprint packages

Optimized for 3.3V systems

Advanced system features

Fast ISP programming times

Port Enable pin for dual function of JTAG ISP pins

2.7V to 3.6V supply voltage at industrial temperature

range

Programmable slew rate control per macrocell

Security bit prevents unauthorized access

Refer to XPLA3 family data sheet (DS012) for

architecture description

Frequency (MHz)

Typical I

48-ball CS BGA (36 user I/O pins)

44-pin VQFP (36 user I/O)

44-pin PLCC (36 user I/O)

Ultra-low power operation

5V tolerant I/O pins with 3.3V core supply

Advanced 0.35 micron five layer metal EEPROM

process

Fast Zero Power™ (FZP) CMOS design

technology

In-system programming

Input registers

Predictable timing model

Up to 23 available clocks per function block

Excellent pin retention during design changes

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Four global clocks

Eight product term control terms per function block

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

vs. Frequency (V

(mA)

0.02

= 3.3V, 25°C)

0.13

0.54

www.xilinx.com

1-800-255-7778

1.06

XCR3032XL 32 Macrocell CPLD

Preliminary Product Specification

Description

The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at

power sensitive designs that require leading edge program-

mable logic solutions. A total of two function blocks provide

750 usable gates. Pin-to-pin propagation delays are 5.0 ns

with a maximum system frequency of 200 MHz.

TotalCMOS Design Technique for Fast

Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technol-

ogy and design technique. Xilinx employs a cascade of

CMOS gates to implement its sum of products instead of

the traditional sense amp approach. This CMOS gate imple-

mentation allows Xilinx to offer CPLDs that are both high

performance and low power, breaking the paradigm that to

have low power, you must have low performance. Refer to

Figure 1

XCR3032XL TotalCMOS CPLD (data taken with two

resetable up/down, 16-bit counters at 3.3V, 25 C).

Figure 1: I

and

2.09

Table 1

vs. Frequency at V

5.2

showing the I

Frequency (MHz)

10.26

100

120

vs. Frequency of our

20.3

200

140

= 3.3V, 25°C

160

DS023_01_080101

180 200

Related parts for DS023

DS023 Summary of contents

Page 1

... R DS023 (v1.6) June 27, 2002 Features • Lowest power 32 macrocell CPLD • 5.0 ns pin-to-pin logic delays • System frequencies up to 200 MHz • 32 macrocells with 750 usable gates • Available in small footprint packages - 48-ball CS BGA (36 user I/O pins) - 44-pin VQFP (36 user I/O) - 44-pin PLCC (36 user I/O) • ...

Page 2

... I (3.3V (3.3V (2.7V) OH 0.5 1 1.5 2 2.5 3 Volts www.xilinx.com 1-800-255-7778 Min. Max. 2.4 - (3) 2 0.4 = GND or V – GND or V – 3.6V - 100 - 0. 3.5 4 4.5 5 DS012_10_031802 DS023 (v1.6) June 27, 2002 Preliminary Product Specification R (1) Unit ...

Page 3

... Specifications measured with one output switching. DS012 2. See XPLA3 family data sheet ( 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS023 (v1.6) June 27, 2002 Preliminary Product Specification -5 Min. Max. 4.5 (3) 5.0 3.5 2.5 - 3 ...

Page 4

... These parameters guaranteed by design and characterization, not testing. DS012 2. See XPLA3 family data sheet ( 4 (1,2) -5 Min. Max. - 0.7 - 2.2 - 0.7 - 1.8 - 4.5 - 1.3 1.0 - 0.3 - 2 1.0 - 2.0 - 3.5 - 2.5 - 2.0 - 2.5 - 0.5 - 2.0 - 1.2 - 4.0 ) for timing model. www.xilinx.com 1-800-255-7778 -7 -10 Min. Max. Min. Max. - 1.6 - 2.2 - 3.0 - 3.1 - 1.0 - 1.3 - 2.7 - 3.6 - 5.0 - 5.7 - 1.6 - 2.0 1.0 - 1.2 - 0.5 - 0.7 - 2.5 - 3.0 - 4 1.3 - 1.6 - 2.3 - 2.1 - 5.0 - 6.0 - 2.7 - 3.3 - 2.7 - 3.3 - 3.2 - 4.2 - 2.9 - 3.5 - 2.5 - 3.0 - 2.0 - 2.5 - 5.0 - 6.0 DS023 (v1.6) June 27, 2002 Preliminary Product Specification R Unit ...

Page 5

... R Switching Characteristics 4.5 4.0 3.5 3 Outputs Figure 4: Derating Curve for T DS023 (v1.6) June 27, 2002 Preliminary Product Specification Component OUT Measurement T POE (High) T POE (Low Note: For T POD output level of V Figure 3: AC Load Circuit +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified ...

Page 6

... PC44 VQ44 CS48 (1) ( 15, 23, 9, 17, 29, B3, C7 E2, G4 22, 30, 42 16, 24, 36 A5, E3 A7, B2, F6, G3 for full explanation. DS023 (v1.6) June 27, 2002 Preliminary Product Specification R CS48 G5 F4 (1) ...

Page 7

... CS48 Component Availability Pins Type Code XCR3032XL -5 -7 -10 DS023 (v1.6) June 27, 2002 Preliminary Product Specification XCR3032XL - Package 44-pin Plastic Lead Chip Carrier (PLCC) 44-pin Very Thin Quad Flat Pack (VQFP) 48-ball Chip Scale Package 44 44 Plastic PLCC ...

Page 8

... OR array. Updated AC Load Circuit diagram SU SU2 Figure 2. Increased -5 T parameter to internal timing model. PTCK www.xilinx.com 1-800-255-7778 Figure 2; added Table 2: Total User 1. changed - 200 MHz SYSTEM ) to AC Table, SU1 delay POD to 6.0 (from 5.5 ns) by PCO DS023 (v1.6) June 27, 2002 Preliminary Product Specification R F ...

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