NJU26040V-16A NJRC [New Japan Radio], NJU26040V-16A Datasheet - Page 6

• Manufacturer Part Number: NJU26040V-16A
• Description: Digital Signal Processor for 2ch Speaker System
• Manufacturer: NJRC [New Japan Radio]

Note: When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
■
■
- 6 -
additional flexibility to a system design by four different SLAVE addresses of the NJU26040-16A. An address can be
arbitrarily set up by the AD1 and AD2 pins. The I
Note : The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I
out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low ( SSb=0 ). Data is
clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte
(MSB) which is latched on the falling transitions of SSb.
resistor when SDOUT is Hi-Z.
I
AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) This offers
SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted
SDOUT is Hi-Z in case of SSb = “High”. SDOUT is Open-drain output in case of SSb = “Low”. SDOUT needs a pull-up
2
I
4-Wire Serial Interface
C bus interface transfers data to the SDA pin and clocks data to the SCL pin.
2
transition of SSb=”High”. When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB
data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”.
C bus
Table 6 I
SSb
SCK
SDIN
SDOUT
bit7
0
0
0
0
2
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
C bus SLAVE Address
Hi-Z
Start
bit
bit6
MSB
bit7
bit7
0
0
0
0
bit6
bit6
bit5
1
1
1
1
Fig.4 4-Wire Serial Interface Timing
Slave Address ( 7bit )
2
C address of AD1/AD2 is decided by connection of AD1/AD2 pins.
bit5
bit5
bit4
1
1
1
1
bit3
1
1
1
1
bit1
bit1
AD2
bit2
0
0
1
1
LSB
bit0
bit0
R/W
bit
unstable
AD1
bit1
0
1
0
1
ACK
2
C bus data transfer.
Hi-Z
R/W
R/W
bit0
Ver.2008-03-06