IDT72V3656 IDT [Integrated Device Technology], IDT72V3656 Datasheet - Page 9

• Manufacturer Part Number: IDT72V3656
• Description: 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
• Manufacturer: IDT [Integrated Device Technology]

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
NOTES:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; T
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
4. Design simulated, not tested.
(For 10ns speed grade only: Vcc = 3.3V
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
DS
SDS
DH
BEH
SDH
SPH
CLK
CLKH
CLKL
ENS1
ENS2
RSTS
FSS
BES
SENS
FWS
RTMS
ENH
RSTH
FSH
SENH
RTMH
SKEW1
SKEW2
Symbol
(3)
(3,4)
Clock Frequency, CLKA, CLKB, or CLKC
Clock Cycle Time, CLKA, CLKB, or CLKC
Pulse Duration, CLKA, CLKB, or CLKC HIGH
Pulse Duration, CLKA, CLKB, OR CLKC LOW
Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑
Setup Time, CSA and W/RA before CLKA↑; CSB
Setup Time, ENA, and MBA before CLKA↑; RENB
and MBB before CLKB↑; WENC and MBC before CLKC↑
Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2
LOW before CLKA↑ or CLKB↑
Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH
Setup Time, BE/FWFT before MRS1 and MRS2 HIGH
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
Setup Time, BE/FWFT before CLKA↑
Setup Time, RTM before RT1; RTM before RT2
Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB,
RENB, and MBB after CLKB↑; WENC and MBC after CLKC↑
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2
LOW after CLKA↑or CLKB↑
Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
Hold Time, FS0/SD after CLKA↑
Hold Time, FS1/SEN HIGH after CLKA↑
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
Hold Time, RTM after RT1; RTM after RT2
Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and
FFA/IRA; between CLKA↑ and CLKC↑ for EFA/ORA and
FFC/IRC
Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA;
between CLKA↑ and CLKC↑ for AEA and AFC
before CLKB↑
±
Parameter
A
(2)
0.15V
= 0° to +70°.
(2)
;
T
A
= 0°C to +70°C; JEDEC JESD8-A compliant)
9
TM
IDT72V3656L10
IDT72V3666L10
IDT72V3676L10
4.5
4.5
7.5
7.5
0.5
0.5
0.5
0.5
Min.
10
12
—
3
4
3
5
3
3
0
5
4
2
2
2
5
5
100
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
COMMERCIAL TEMPERATURE RANGE
Min.
IDT72V3656L15
IDT72V3666L15
IDT72V3676L15
4.5
4.5
8.5
7.5
7.5
15
12
—
6
6
4
5
4
4
0
5
1
1
4
2
2
1
1
2
5
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns