cxa1166k Sony Electronics, cxa1166k Datasheet - Page 11

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cxa1166k

Manufacturer Part Number
cxa1166k
Description
8-bit 250 Msps Flash A/d Converter
Manufacturer
Sony Electronics
Datasheet
• Unlike the CXA1176, V
• Although V
• OR and OR are output pins for indicating that the input is over range. They are not inverted by MINV or LINV.
• Noise in MINV and LINV results in misoperation, the cause of which is extremely difficult to track down. Keep
• Inputting differential signals is recommended for the CLK and CLK clock input pins. Although operation is
• When the CLK pin is not used, by-pass it to DGND using a capacitor (approximately 0.1µF). At this time,
• This converter is designed to be used at the clock duty cycle of 50%. The deviation from this condition will
• Increasing chip temperature will cause the supply current and also the error rate to rise. Adding to these
• Since the CXA1166K is a high-speed IC, take adequate measures to prevent electrostatic breakdown. For
• Sony’s SPECL series is used as the logic ICs in the Application Circuit to investigate the maximum
500 . Since these resistors may be eliminated in the future improved versions of this converter, use a
reference voltage generation circuit which is adaptable to their elimination. The reference voltage generation
circuit (the section composed of IC12_2, etc.) in the Application Circuit is recommended.
compensation. It is recommended that it is kept open.
these pins open in cases where low level setting voltage alone is sufficient. When high level voltage input is
required, provide the shortest possible by-pass from them to DGND using chip capacitors (approximately
0.1µF). Input voltages of –0.5V to –1.0V for high level and –1.6V to –2.5V for low level are recommend. Do
not make the direct connection to DGND when high level voltage is input.
possible by driving only the CLK pin, doing so involves the risk that the characteristics may become unstable
near the maximum speed. This is because the internal operation of the A/D converter depends on both clock
rise and fall.
approximately –1.3V voltage will be generated at this pin. However, the driving capacity is too weak for this to
be used as the V
subtly affect the performance of the A/D converter but the degree of the affection is not so great as to require
adjustment. The “Error rate vs. Clock duty cycle characteristics” graph shows an example of these changes
in the converter’s performance.
reasons, in order to prolong the converter’s service life, provide an adequate means of cooling. See the
“Maximum conversion frequency vs. Temperature characteristics” and “Supply current vs. Temperature
characteristics” graphs. The reference data for thermal resistance is shown in the “Thermal resistance of the
converter mounted on a board” graph. Note that the actual thermal resistance will differ greatly depending on
the mounting conditions.
further details on these measures, refer to “Precautions for IC Application” in Sony’s Data book.
performance of the CXA1166K. For normal applications, lower speed logic ICs can be used according to the
applied frequency.
RM
is provided to compensate for the integral linearity error, there is no need for such
BB
threshold voltage. It cannot drive even one ECL input load.
RTS
and V
RBS
are connected to the reference resistors via resistors of approximately
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CXA1166K

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