cxa1396d Sony Electronics, cxa1396d Datasheet
cxa1396d
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cxa1396d Summary of contents
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... MSPS Flash A/D Converter Description The CXA1396D are 8-bit ultrahigh-speed flash A/D converter ICs capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of these A/D converters are compatible with the ECL 100K/10KH/10K. The CXA1396D is pin-compatible with the earlier model CX20116. They can replace the earlier models respectively, without any design changes, in most cases ...
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... V 2.5 RB –4 to +0.5 2.7 – – –65 to +150 Min. Typ –5.5 –5.2 EE – DV –0. –0.05 0 –0.1 0 –2.2 –2 4.0 4.0 –20 – 2 – CXA1396D °C Max. unit –4.95 V +0.05 V +0.05 V +0.1 V –1 +75 °C ...
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... r CLK CLOCK DRIVER CLK MINV 1 2 • • • • • • 126 127 128 129 • • • 191 192 193 • • • 254 255 LINV – 3 – CXA1396D D7 (MSB (LSB) ...
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... Equivalent circuit DGND1 CLK CLK – 4 – CXA1396D Description Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. Analog –5.2V (Typ.). Internally connected with DV EE (resistance ceramic chip capacitor of at least 0.1µ ...
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... MINV –1. AGND – 5 – CXA1396D Description LSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required. MSB of data outputs. External pull-down resistor is required. Input pin for D0 (LSB output polarity inversion (see output code table) ...
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... Comparator 255 – 6 – CXA1396D Description Reference voltage (bottom). Typically –2V. A ceramic capacitor of at least 0.1µF and a tantalum capacitor of at least 10µF should be used to connect to AGND near the pins. Reference voltage mid point. Can be used as a pin for integral linearity compensation ...
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... 2Vp-p, 3dB down IN Input = 1MHz Clock = 125MHz Input = 31.5MHz Clock = 125MHz { Input = 31.249MHz, FS Error > 16LSB Clock = 125MHz NTSC 40IRE mod.ramp 125MSPS – 7 – CXA1396D = –5.2V 0V –2V Min. Typ. Max. Unit 8 bits ±0.3 ±0.5 LSB ±0.3 ±0.5 LSB ...
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... Tpw0 80% N – 1 20% Tr – 8 – CXA1396D …… …… …… ...
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... S1 –V A < > B Comparator 8 8 DUT A8 B8 CXA1396D "0" "1" CLK (125MHz) Controller – 9 – CXA1396D A Comparator Pulse Counter (CX20202A-1) 8 10bit D/A Delay Vector Scope DG. Buffer 00000000 8 to 11111110 ...
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... Apeature jitter is defined as follows: v 256 Taj = / = /( t Where (unit : LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. – 10 – CXA1396D 0V –1V –2V 129 (LSB) 128 t 127 126 125 ...
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... ADC Evaluation board Description The CXA1396D EVALUATION BOARD WITH DAC is a tool for customers to evaluate the performance of the CXA1396D (8-bit, 125MSPS, high-speed A/D converter). In addition to indispensable features such as the reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high-speed DAC, and the 20-pin cable connector for digital outputs ...
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... CXA1396D …… …… … ...
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... PCB output pin CLK (For 1/1 frequency division) PCB output pin N – 4 DATA OUT (For 1/2 frequency division) CLKN PCB output pin CLK (For 1/2 frequency division – – 2 Tdh 1.8ns (Typ) N – 2 Tdh 1.8ns (Typ) – 13 – CXA1396D N N – ...
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... SW4 (D/A INV) The switch for D/A converter output inversion Input through the Input through the capacitor B buffer amplifier (When the offset is adjusted using the C (When the linearity DIR IN. at the evaluation board adjusted) 0.1µF – 14 – CXA1396D ...
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... A/D converter outputs. Those are inverted again in the D/A converter so that the direction of reproduced waveform can agree with the A/D input signal converter. 13) The part unmber of the digital output connector is KEL 8830E-020-170S. A corresponding connector and cable assembly is JUNKOSMA KBO020MCG50BI. 1.2mm GND Probe point 300mil Fig. 3 – 15 – CXA1396D ...
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... S2 Rn1 C14 C10 51 0.1µ C13 0.1µ 0.1µ Rn1 C5 –5.2V (D) –2V DGND DGND 0.1µ DGND DGND (D) DGND – 16 – CXA1396D P8 R17 CLK CLKN 51 C22 R16 0.1µ 51 DGND –2V (D) P16 P17 D6 D7 P17 –5.2V ( P14 P15 D4 D5 DGND P6 C26 1µ ...
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... DGND –2V (D) 11 Rn7 51 12 Rn7 CLKN P20 DGND 51 13 Rn7 CLK P19 51 14 Rn7 C43 51 0.1µ Rn7 –2V (D) DGND – 17 – CXA1396D –2V (D) CONNECTOR C53 0.1µ KEL: 8830E-020-170S (TOP VIEW) DGND Rn12 Rn12 DGND D0 Rn12 DGND Rn12 5 6 ...
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... DIR the characteristic where the signal is directry input to the ADC and AMP the characteristic where the signal is input to ADC through the amplifier. Fig. 5. Gain vs. Input frequency (CLK = 125MHz) 10 100 Input frequency [MHz] Fig. 6. SNR vs. Input frequency (CLK = 125MHz) 10 Input frequency [MHz] (CLK = 125MHz) 10 Input frequency [MHz] – 18 – CXA1396D DIR. IN AMP. IN 100 100 ...
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... Parts Layout – 19 – CXA1396D ...
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... Printed Pattern 1st layer Component plane (Top View) 4th layer Solder plane (Top View) – 20 – CXA1396D ...
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... GND plane (Top View) 3rd layer Power supply plane (Top View) – 21 – CXA1396D ...
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... Package Outline Unit SONY CODE EIAJ CODE JEDEC CODE 42PIN DIP (CERAMIC) 600mil 53.4 ± 0.5 13.2 ± 0 2.54 0.46 ± 0.1 1.0 ± 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL DIP-42C-01 LEAD TREATMENT DIP042-C-0600-A LEAD MATERIAL PACKAGE WEIGHT – 22 – CXA1396D 0° to 15° CERAMIC GOLD PLATING 42 ALLOY 6.7g ...