lc72136nm Sanyo Semiconductor Corporation, lc72136nm Datasheet - Page 11

• Manufacturer Part Number: lc72136nm
• Description: Pll Frequency Systhesizer
• Manufacturer: Sanyo Semiconductor Corporation

Continued from preceding page.
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No.
(6)
(7)
(8)
(9)
DO pin control data
DOC0, DOC1, DOC2
Unlock detection data
UL0, UL1
Phase comparator
control data
DZ0, DZ1
Clock time base
TBC
Charge pump control data
DLC
Control block/data
• Data that determines DO pin output
Caution: The DO pin always goes to the open state during the data input period (during the
• Selects the phase error (øE) detection range for PLL lock discrimination.
• Phase comparator dead zone control data
• An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1.
• Data that forcibly controls the charge pump output
The open state is selected following a power-on reset.
Note: 1. end-UC: IF counter measurement completion check
When a phase error greater than the specified range occurs, the LC72136N determines
that the PLL is unlocked. (*: Don’t care.)
Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0.
Dead zone width: DZA < DZB < DZC < DZD
(The BO1 data will be ignored.)
Note: The LC72136N provides a technique for escaping from deadlock by setting Vtune to
This function goes to the forced low state (DLC = 1) following a power on reset.
The crystal oscillator circuit must be operating normally before this data is changed to
return to the normal operating (DLC = 0) state.
DOC2
UL1
DZ1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
2. Goes to the open state if the IO pin itself is set to be an output port.
V
VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V.
period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin
control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal
DO serial data in synchronization with the CL pin signal during the data output period
(during the period when CE is high in the OUT mode) regardless of the values of
the DO pin control data (DOC0 to DOC2).
DLC
CC
0
1
(deadlock clearing circuit). This is used when the circuit is deadlocked due to the
DOC1
When end-UC is set and an IF count is started (CTE = 0
When the IF count measurement completes, the DO pin goes low and
The DO pin goes to the open state due to serial data I/O (CE: high).
UL0
DZ0
automatically goes to the open state.
the count completion check operation is enabled.
0
0
1
1
0
0
1
1
0
1
*
0
1
0
1
Stopped
0
±6.67 µs
DZA
DZB
DZC
DZD
Normal operation
Forced low
DOC0
LC72136N, 72136NM
0
1
0
1
0
1
0
1
øE detection width
Open
Low when the unlock state is detected
end-UC
Open
Open
The IO1 pin state
The IO2 pin state
Open
Description
*1
Charge pump output
Dead zone mode
*2
*2
DO pin state
Open
øE is output directly
øE is extended by 1 to 2 ms
Detector output
1), the DO pin
Continued on next page.
UL0, UL1,
CTE,
IOC1, IOC2
DOC0,
DOC1,
DOC2
BO1
Related data
No. 5608-11/23