AD6140ARSRL AD [Analog Devices], AD6140ARSRL Datasheet - Page 2

• Manufacturer Part Number: AD6140ARSRL
• Description: Bandpass IF Subsystem
• Manufacturer: AD [Analog Devices]

Specification
OVERALL
AGC DETECTOR
ECL-TO-CMOS LEVEL
LNA BIAS AMPLIFIER VOLTAGE
POWER-DOWN INTERFACE
POWER SUPPLY
Specifications subject to change without notice.
AD6140–SPECIFICATIONS
Input Third Order Intercept Point
Noise Figure
Input Resistance
Input Capacitance
Dynamic Range
Maximum Gain
Minimum Gain
AGC Threshold
Capacitor Charging Current
TRANSLATOR
LNA_FORCE
LNA_SENSE Input Voltage Range
Logic Threshold
Turn-On Response Time
Turn-Off Response Time
Supply Voltage
Supply Current
Power-Down Current
Operating Temperature Range
Clock Output Drive
Clock Asymmetry
Conditions
VOLTAGE_REFERENCE_IN = 1 V
IF = 49.6 MHz
LO = 49.792 MHz or 49.408 MHz, 200 mV p-p
Clock = 6.144 MHz, 800 mV p-p Differential ECL
At Max Gain
At Max Gain, External Termination
At IF_INPUT (Pin 19)
At IF_INPUT (Pin 19)
6.25 kHz Bandwidth Centered at 192 kHz
AGC_TC_SELECT Input = Logic LOW (FAST AGC)
AGC_TC_SELECT Input = Logic HIGH (SLOW AGC)
VDD (to VDD – 0.8 V) Differential Levels
5 pF Load
5 pF Load
2.9 V LNA_SENSE, Minimum Gain
To Valid Data Output
To Typical Power-Down Supply Current
Power-Down Input: Logic LOW = ON, IF_Input = 0 V
Power-Down Input: Logic HIGH = OFF
Differential Input
Input, Clock Asymmetry = 50
(T
A
= +25 C, V
–2–
CC
= 2.7 V, VOLTAGE_REFERENCE_IN = 1 V, unless otherwise noted)
2.5%
5% dc,
–27
76
2.6
1.7
VDD
2.5
–40
Min
–19
10.5
2.5
12
83
29.5
16
–24
2.8
50
0.7
100
100
4.8
3
Typ Max
2.5
VDD – 0.3
2.9
+85
5.75
REV. 0
Units
dBm
dB
k
pF
dB
dB
dB
dBm
nA
V p-p
%
V
V
V
V
mA
C
A
s
s
A