AD6140ARSRL AD [Analog Devices], AD6140ARSRL Datasheet - Page 8

• Manufacturer Part Number: AD6140ARSRL
• Description: Bandpass IF Subsystem
• Manufacturer: AD [Analog Devices]

AD6140
LEVEL DIAGRAM
Figure 10 shows a simplified block diagram of the AD6140 with
the expected signal levels for the minimum gain configuration.
f = 49.6MHz
60mV p-p
IF INPUT
PREAMPLIFIER
–16.3 dBm REFERRED TO 50
OSCILLATOR INPUT
49.792MHz
Figure 10. Level Diagram
MIXER
LOCAL
DETECTOR
CIRCUIT
AGC
Tx/Rx
SW
MIXER POST
AMPLIFIER
986-902MHz
1 WATT
2.4V HBT
LNA
PA
0.078 (1.98)
0.068 (1.73)
AGC
929-941MHz SC-4344-A
0.008 (0.203)
0.002 (0.050)
MODULATOR
PIN 1
FILTER
SAW
Figure 11. ReFLEX Transceiver Block Diagram
Tx DATA
20
1
MODULATOR
TRF9506
0.0256
(0.65)
I/Q
0.295 (7.50)
0.271 (6.90)
BSC
Dimensions shown in inches and (mm).
378mV p-p
AT 192kHz
OUTLINE DIMENSIONS
DATA OUT
49.6MHz
FILTER
SEATING
XTAL
20-Lead SSOP
PLANE
0.066 (1.67)
10
11
0.07 (1.78)
REF CLK
76.8MHz
(RS-20)
0.212 (5.38)
0.205 (5.21)
–8–
SYNTHESIZER
FREQUENCY
0.009 (0.229)
0.005 (0.127)
MC145181
Motorola ReFLEX Transceiver
Figure 11 shows a block diagram of the Motorola ReFLEX
chipset solution including the AD6140. As can be seen, the
AD6140 accepts an IF input from a crystal filter at 49.6 MHz.
The frequency synthesizer provides the 6.144 MHz clock, while
the LO is also generated from the frequency synthesizer but is
fed to the AD6140 via the I/Q modulator. The IF data output
and the clock output both feed into the IF data processor. The
LNA bias amplifier provides the AGC voltage for the first LNA
in the receive path. The dc power is supplied from the power
management chip.
0.301 (7.64)
0.311 (7.9)
AD6140
A/D
8
0
6.144MHz
SAMPLING
CLK
IF DATA
CLOCK
2.8V DV
2.7V AV
BATTERY
PRIMARY
0.022 (0.559)
0.037 (0.94)
PROCESSOR
DD
DD
IF DATA
PWR MGT
MAX847
TRANSMIT
SOURCE
POWER
SPI TO
REFLEX
CODEC
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