74HCT00D,652 NXP Semiconductors, 74HCT00D,652 Datasheet

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Quad 2-input NAND gate Rev. 5 — 25 November 2010 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The ...

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... NXP Semiconductors 4. Functional diagram mna212 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74HC00 74HCT00 GND Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 10, 13 74HC_HCT00 Product data sheet 1 3 & & & & 13 mna246 Fig 2 ...

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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin GND Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions ...

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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance 74HCT00 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage = 20  4 LOW-level output voltage = 20  5.2 mA input leakage ...

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... NXP Semiconductors Table 7. Dynamic characteristics GND = pF; for load circuit see L Symbol Parameter Conditions C power dissipation per package capacitance 74HCT00 t propagation delay nA nY; see transition time power dissipation per package; PD capacitance the same as t and PHL PLH [ the same as t and t ...

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... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74HC00 V CC 74HCT00 3.0 V 74HC_HCT00 Product data sheet ...

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... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

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... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

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... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 10. Package outline SOT337-1 (SSOP14) ...

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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74HC_HCT00 v.5 20101125 • ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT00 Product data sheet 15 ...

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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations ...