cxa2025as Sony Electronics, cxa2025as Datasheet
cxa2025as
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cxa2025as Summary of contents
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... Y/C/RGB/Sync/Deflection for Color TV Description The CXA2025AS is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for NTSC system color TVs onto a single chip. The following functions have been added to the same function IC, CXA2025S ...
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... CC – 2 – CXA2025AS CC ...
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... Provide a bias of about V signal (including sync, 100% white, 2Vp-p CV 30k signal) with a 570mVp-p burst level. 35µ Power supply for the video block 50µ bus protocol SCL (Serial Clock) input. VILMAX = 1.5V VIHMIN = 3.5V 10k – 3 – CXA2025AS Description /2 and input ...
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... Y) signal via a capacitor. The signal is clamped to 6.2V at the burst timing of the signal input to the sync input pin (Pin 44). GND for the video block switch control input. 100µ When YM is high, the Y/C block signal is attennated by 6dB. VILMAX = 0.4V VIHMIN = 1.0V 40k VIHMAX = 3.0V – 4 – CXA2025AS Description ...
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... High voltage compensation has linear control characteristics for the pin voltage range of about 147 3V to 1V. ABL does not operate when the pin voltage is 9 [V], and operates with increasing strength as the voltage becomes lower than 9 [V]. – 5 – CXA2025AS Description ...
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... VDRIVE–. The Vprotect function can 30k also be operated by this pin. 24k 400µ 1.4k 25µ V parabola wave output. 15k 78k 800µ Sample-and-hold for AGC which maintains the V 1.2k sawtooth wave at a constant amplitude. Connect to GND via a capacitor. – 6 – CXA2025AS Description 2 C bus. ...
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... JV CC 46k CR connection for the AFC lag-lead filter. 50µ 50µ 10k Connect the 32f 400µ 50µ GND for the deflection block. – 7 – CXA2025AS Description 2 C bus. VCO ceramic oscillator. H ...
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... Burst gate pulse output. This pulse positive polarity pulse. While this pulse is gated near V-Sync for the CXA2025S constantly output for the 15k CXA2025AS. 1k Not connected. Normally connected to GND to prevent interference with other pins. – 8 – CXA2025AS Description control. 0 ...
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... CXA2025AS ...
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... CXA2025AS ...
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... CXA2025AS ...
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... CXA2025AS ...
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... SUB-CONT = 7 Hex SUB-COLOR = 7 Hex SUB-BRIGHT = 1F Hex G-DRIVE = 2A Hex AGING2 = 0 G-CUTOFF = 0 EY- RON = 1 BON = 1 VOFF = 0 CD-MODE = 0 V-SIZE = 1F Hex V-POSITION = 1F Hex S-CORR = 0 H-SIZE = 1F Hex PIN-COMP = 1F Hex H-POSITION = 7 Hex UP-CPIN = 0 AFC-BOW = 7 Hex V-ASPECT = 0 Hex HBLKSW = 0 JMPSW = 0 LO-VLIN = 0 Hex RIGHT-BLK = 7 Hex – 13 – CXA2025AS ...
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... CXA2025AS ...
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... Electrical Characteristics Measurement Circuit Signal sources are all GND unless otherwise specified in the Measurement conditions column of Electrical Characteristics. ABL is 9V unless otherwise specified. – 15 – CXA2025AS ...
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... V-SIZE V-POSITION S-CORR H-SIZE PIN-COMP H-POSITION UP-CPIN AFC-BOW V-ASPECT V-SCROLL UP-VLIN LEFT-BLK BIT4 BIT3 BIT6 BIT5 IKR VNG HNG KILLER – 16 – CXA2025AS BIT2 BIT1 BIT0 C-TRAP VM DC-TRAN D-PIC TOT AXIS D-COL ABL PRE-OVER SHP-F0 CTRAP-ADJ SUB-HUE GAMMA AGING1 AGING2 EY-SW CD-MODE2 ...
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... R-Y, G-Y axis selector switch 0 = Japan axis R-Y: 95° axis RGB output: 2.4Vp-p (I/O gain: +4.7dB, 1.4Vp-p input) Flesh color appears red. Flesh color appears green Point of inflection: 30 IRE B output: 1.1Vp-p (I/O gain: +5.7dB, 0.57Vp-p input) 0.78, G-Y: 240° 0.3 R-Y: 112° 0.83, G-Y: 252° 0.3 (B-Y: 0° 1) – 17 – CXA2025AS ...
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... CTRAP-ADJ (4) : Chroma trap f0 adjustment (Y block chroma trap current control +300kHz 7H = 0kHz FH = –300kHz fsc adjustable to –30dB or less (SHP-F0 min.); adjustment value SUB-COLOR (4) : Color gain control (ACC reference level control –4.0dB 7H = 0dB FH = +2.1dB –300mV from REF-P level (PRE:OVER) – 18 – CXA2025AS ...
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... Vertical sync pull-in speed switch 0 = Standard (equivalent to CXA2025S High speed B-Y axis adjustable to 0° –300mV from REF-P level –3.8dB 0dB +2.5dB 60 IRE flat signal output from Y block when input signal present. –3.8dB 0dB +2.5dB when Pin 9 = high.) when Pin 9 = high.) – 19 – CXA2025AS ...
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... Non-standard signal mode, standard signal mode and no signal mode 1 = Fixed to non-standard signal mode (G/R) (B/R) vary according to V-POSITION.) automatically selected (V oscillator frequency is 55Hz during no signal mode (free run).) – 20 – CXA2025AS AFC normal mode Oscillator frequency fixed to maximum value (16.252kHz). ...
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... Picture position drops, VDRIVE+ output DC Down. Center DC: 3V Picture position rises, VDRIVE+ output DC Up. Maximum compressed. picture expanded. Horizontal picture size decreases, EWDRIVE output DC Down. Amplitude: 0.58Vp-p, center when V-ASPECT is 2FH Horizontal picture size increases, EWDRIVE output DC Up. – 21 – CXA2025AS ...
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... Horizontal size for top of picture decreases (Compensation amount maximum). Horizontal size for bottom of picture increases (Compensation amount minimum). (0.7Vp-p, 4:3 mode) Horizontal size for bottom of picture decreases (Compensation amount maximum). respect to picture center. respect to picture center. – 22 – CXA2025AS ...
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... V-ASPECT. The V blanking width is expanded at both the top and bottom of the picture. Blanking for the bottom of the picture starts 251H after VTIM, and blanking for the top of the picture can be varied as the blanking width after the reference pulse from the VBLKW register. – 23 – CXA2025AS ...
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... Killer OFF status 1 = Killer ON status Note) The following have been added to the CXA2025S. EY-SW: Sub Add 09H, Bit 1 CD-MODE2: Sub Add 09H, Bit 0 HBLK width maximum Center HBLK: 13µs HBLK width minimum HBLK width maximum Center HBLK: 13µs HBLK width minimum – 24 – CXA2025AS ...
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... Description of Operation 1. Power-on sequence The CXA2025AS does not have an internal power-on sequence. Therefore, all IC operations are controlled by 2 the set microcomputer (I C bus controller). 1) Power-on The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized to the input signal ...
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... Bch video output OFF RGB all blanked Vdrive oscillation stopped Horizontal oscillator frequency standard V countdown auto mode AKB ON Center (Adjust) Vertical high voltage fluctuation compensation amount max. Center (Adjust) Center Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) – 26 – CXA2025AS ...
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... F Hex 2. Various mode settings The CXA2025AS contains bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once deflection adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data. • ...
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... In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2025AS also has a register (H-SIZE) which controls the H size, but the control width is not sufficient for 25% compression. Therefore, external measures must be taken such as switching the H deflection coil, etc. ...
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... V-ASPECT = 3FH JMPSW = 1 3. Signal processing The CXA2025AS is comprised of sync signal processing, H deflection signal processing, V deflection signal processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I 1) Sync signal processing The Y signals input to Pins 43 and 44 are sync separated by the horizontal and vertical sync separation circuits ...
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... IRE burst level demodulates a 258mVp-p chroma signal at orthogonal coordinates to become a 0.8 times signal (R-Y is demodulated by the 90° axis to become a 1.14 times signal, B-Y is demodulated by the 0° axis to become a 2.03 times signal bus register (EY-SW). In other words, the YUV – 30 – CXA2025AS ...
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... When designing the board pattern for the CXA2025AS, interference from around the power supply and GND should be considered as the RGB and deflection signals output from the CXA2025AS are DC direct connected. Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the by- pass capacitor which is inserted between the power supply and GND as near to the pin as possible ...
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... Time [ms] 3.6 3.4 3.2 3.0 2.8 VSIZE = 0 2.6 VSIZE = 1F VSIZE = 3F 2 3.6 3.4 3.2 3.0 2.8 SCORR = 0 2.6 SCORR = 7 SCORR = F 2 3.8 3.6 3.4 3.2 3.0 2.8 VASPECT = 0 2.6 VASPECT = 1F VASPECT = 3F 2 – 32 – CXA2025AS V-POSITION V-POSITION = 0 V-POSITION = 1F V-POSITION = Time [ms] V-LIN VLIN = 0 VLIN = 7 VLIN = Time [ms] V-SCROLL VSCROLL = 0 VSCROLL = 1F VSCROLL = Time [ms] ...
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... PIN-COMP = 3F 3 Time [ms] LO-CPIN 4.1 4.0 3.9 3.8 3.7 3.6 LO-CPIN = 0 3.5 LO-CPIN = 7 LO-CPIN = F 3 Time [ms] LO-VLIN 3.6 3.4 3.2 3.0 2.8 2.6 2 Time [ms] PIN-PHASE 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3 Time [ms] UP-CPIN 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3 Time [ms] – 33 – CXA2025AS LO-VLIN = 0 LO-VLIN = 7 LO-VLIN = PIN PHASE = 0 PIN PHASE = 7 PIN PHASE = UP-CPIN = 0 UP-CPIN = 7 UP-CPIN = ...
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... SHARPNESS = 0 –15 SHARPNESS = 7 SHARPNESS = F – Frequency [MHz] COLOR –5 –10 COLOR OFF when DATA = 0 –15 (–40dB or less) – – 34 – CXA2025AS SYNC center µ µ µ DATA ...
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... BRIGHT control characteristics 0.25 0 –0.5 –1 GAMMA control characteristics 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1 YIN input amplitude [IRE] – 35 – CXA2025AS SUB CONT DATA SUB-BRIGHT = 3F SUB-BRIGHT = 1F SUB-BRIGHT = DATA GAMMA 0 GAMMA 1 GAMMA 2 GAMMA ...
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... Cut-off control characteristics 4.0 3.5 Rch 3.0 Gch, Bch IK clamp level 2 DATA AKB open loop characteristics 4 3.5 3 2.5 2 1 Voltage applied to Rch, Gch and Bch sample-and-hold capacitance pins [V] – 36 – CXA2025AS ...
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... SONY CODE EIAJ CODE JEDEC CODE 48PIN SDIP (PLASTIC) 600mil + 0.4 – 0 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SDIP-48P-02 SDIP048-P-0600-A LEAD MATERIAL PACKAGE WEIGHT – 37 – CXA2025AS 0° to 15° EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 5.1g ...