em78p134n ELAN Microelectronics Corp, em78p134n Datasheet - Page 18

• Manufacturer Part Number: em78p134n
• Description: 8-bit Microcontroller With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

EM78P134N
8-Bit Microcontroller with OTP ROM
12 •
5.1.16 RF (Interrupt Status Register)
“1” means there is an interrupt request
Bits 7 ~ 5 (Unused): Unused bits, set to 0 all the time.
Bit 4 (PWMIF): PWM (Pulse Width Modulation) interrupt flag. Set when a selected
Bit 3 (CMPIF): Comparator interrupt flag. Set when a change occurs in the
Bit 2 (EXIF): External interrupt flag. Set by a falling edge on the /INT pin, reset by
Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input changes,
5.1.17 R10 ~ R3F
5.2 Special Purpose Registers
5.2.1 A (Accumulator)
5.2.2 CONT (Control Register)
Bit 7 (INTE): INT signal edge
Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows, reset by software.
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
Bit 6 (INT): Interrupt enable flag
INTE
Bit 7
Bit 7
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
Note that the result of reading RF is the "logic AND" of RF and IOCF.
All of these are 8-bit general-purpose registers.
0
Bit 6
Bit 6
0: interrupt occurs at a rising edge of the INT pin
1: interrupt occurs at a falling edge of the INT pin
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
INT
0
duration is reached. Reset by software.
Comparator output. Reset by software.
software.
reset by software.
Bit 5
Bit 5
TS
0
PWMIF
Bit 4
Bit 4
TE
(This specification is subject to change without further notice)
“0” means no interrupt occurs.
CMPIF
PSTE
Bit 3
Bit 3
Product Specification (V1.6) 06.02.2010
PST2
EXIF
Bit 2
Bit 2
PST1
Bit 1
Bit 1
ICIF
PST0
TCIF
Bit 0
Bit 0