em78p134n ELAN Microelectronics Corp, em78p134n Datasheet - Page 28

• Manufacturer Part Number: em78p134n
• Description: 8-bit Microcontroller With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

EM78P134N
8-Bit Microcontroller with OTP ROM
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5.5 Reset and Wake-up
5.5.1 Reset
Input Status Change
(1) Power-on reset
(2) /RESET pin input "low"
(3) WDT time-out (if enabled)
The device is kept in a reset condition for a period of approximately 18 ms
oscillator start-up timer period) after a reset is detected. Once a reset occurs, the
following functions are performed.
Sleep (power down) mode is attained by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be waken up by:
(1) External reset input on the /RESET pin
(2) WDT time-out (if enabled), or
(3) Port 6 input status changes (if enabled).
The first two cases will cause the EM78P134N to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up). The last case is considered a
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the interrupt vector address after a wake-up. If DISI is executed before
SLEP, the operation will restart from the instruction right next to SLEP after a wake-up.
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Vdd = 5V, set up time period = 16.5ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).
The bits of the IOCB register are set to all "1".
The IOCC register is cleared.
The bits of the IOCD register are set to all "1".
Bit 7 of the IOCE register is set to "1", and Bits 6~0 are cleared
Bits 0 ~ 4 of RF and Bits 0 ~ 4 of IOCF register are cleared.
(This specification is subject to change without further notice)
Product Specification (V1.6) 06.02.2010
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