em78p131a ELAN Microelectronics Corp, em78p131a Datasheet - Page 26

• Manufacturer Part Number: em78p131a
• Description: 8-bit Microcontroller With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

EM78P131A
8-Bit Microcontroller with OTP ROM
22 •
5.6 Interrupt
The EM78P131A has three falling-edge interrupts as listed herewith:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin]
Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV
R6,R6") is necessary. Each pin of Port 6 will have this feature if its status changes.
Any pin configured as output or P60 pin configured as /INT, is excluded from this
function. The Port 6 Input Status Changed Interrupt can wake up the EM78P131A from
Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing SLEP
instruction. When the chip wakes-up, the controller will continue to execute the
program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will
branch to the interrupt Vector 008H.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from Address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Fig. 5-10). The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from Address 001H.
Figure 5-10 Interrupt Input Circuit
(This specification is subject to change without further notice)
Product Specification (V1.2) 09.16.2009