ml9289 Oki Semiconductor, ml9289 Datasheet - Page 14

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ml9289

Manufacturer Part Number
ml9289
Description
Vacuum Fluorescent Display Tube Controller Driver
Manufacturer
Oki Semiconductor
Datasheet

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*1 When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally
Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from
“High” to “Low” is recognized in 8-bit units.
Reset Function
Reset is executed when the RESET pin is set to “L”, (when turning power on, for example) and initializes all
functions.
Initial status is as follows.
• Address of each RAM .......................Address 00H
• Data of each RAM ............................All contents are undefined.
• Number of display digits ...................16 digits
• Brightness adjustment .......................0/16
• All display lights ON or OFF............OFF mode
• Segment output..................................All segment outputs go “Low.”
• AD output..........................................All AD outputs go “Low.”
Be sure to execute the reset operation when turning power on and set again according to “Setting Flowchart”
after reset.
When data is written
to DCRAM(*1)
incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the
2nd and subsequent bytes.
CS
CP
DA
B0 B1 B2 B3 B4 B5 B6 B7
LSB
Command and address
data
1st byte
MSB
t
DOFF
B0 B1 B2 B3 B4 B5 B6 B7
LSB
Character code data
2nd byte
MSB
LSB
B0 B1 B2 B3 B4 B5 B6 B7
Character code data of
the next address
3rd byte
MSB
FEDL9289-01
ML9289-xx
t
CSH
14/31

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