cxd2589q Sony Electronics, cxd2589q Datasheet
cxd2589q
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cxd2589q Summary of contents
Page 1
... CD Digital Signal Processor Description The CXD2589Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters, zero detection circuit, 1-bit DAC, and analog low-pass filter on a single chip. Features Digital Signal Processor (DSP) Block • Playback mode supporting CAV (Constant Angular Velocity) – ...
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... Error Corrector D/A EFM Interface 16K RAM Digital OUT Digital CLV – 2 – CXD2589Q TES1 TEST 23 79 XRST 3 RMUT 2 Serial-In LMUT Interface 70 XTAI Timing Logic 71 XTAO Over Sampling Digital Filter ...
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... AVss 78 XRST – 3 – CXD2589Q LRCKI 39 LRCK 38 ASYO 37 ASYI 36 BIAS CLTV 32 AVss 31 FILI 30 FILO 29 PCO 28 VCTL ...
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... Master PLL (slave = digital PLL) filter output. 30 FILO O Analog Master PLL filter input. 31 FILI I Analog GND — — SS Master VCO control voltage input. 33 CLTV I Analog power supply (+5V — — DD EFM signal input Description – 4 – CXD2589Q ...
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... Left-channel operational amplifier input. 66 AIN1 I Left-channel LINE output. 67 LOUT1 O Analog GND — — SS Power supply for master clock Crystal oscillation circuit input. Input the external master clock via this pin. 70 XTAI I Crystal oscillation circuit output. 71 XTAO O Description , high = – 5 – CXD2589Q ...
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... GFS goes high when the frame sync and the insertion protection timing match. • RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed). • C2PO represents the data error status. • XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin. Description – 6 – CXD2589Q ...
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... I = –0.28mA ( 0.36mA – 5.50V – 5.50V LO O and AV , respectively – 7 – CXD2589Q = 0V, Topr = –20 to +75°C) SS Applicable Typ. Max. Unit pins ...
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... Min. Typ. Max. Unit 15 34 MHz = AV = 5.0V ± 5 Min. Typ. Max. Unit ns 13 500 13 500 ns 1,000 ns 26 – WLX WHX 5.0V ± 5 Min. Typ. Max. Unit 2 0.3 Vp-p DD – 8 – CXD2589Q V IHX V 0.9 IHX 0.1 IHX V ILX ...
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... WCK 1 5.0V ± 5 Typ. Min (BCKI) t (BCKI (PCMDI) (PCMDI (LRCKI) – 9 – CXD2589Q = 0V, Topr = –20 to +75°C) SS Max. Unit ...
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... Analog Characteristics ( Conditions Crystal 384Fs 768Fs 384Fs 768Fs 680p 12k 22µ 100k LPF External Circuit Diagram 768Fs/384Fs Rch RF CXD2589Q Lch – 10 – CXD2589Q = 5.0V 0V 25° Min. Typ. Max. Unit 0.0050 0.0070 % 0.0045 0.0065 96 100 dB 96 100 SHIBASOKU (AM51A) ...
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... OUT Load resistance R L Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is output. Applicable pins 1 LOUT1, LOUT2 ( 5.0V 0V, Topr = – +75° Min. Typ. Max. 1.12 8 – 11 – CXD2589Q Unit Applicable pins Vrms ...
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... Information on each address and the data is provided in Table 1-1. • The internal registers are initialized by a reset when XRST is low; the initialization data is shown in Table 1-2. Note) When XLAT is low, SQCK must be set high Data Address – 12 – CXD2589Q 750ns or more Valid 300ns max ...
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... Register – 13 – CXD2589Q ...
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... Register – 14 – CXD2589Q ...
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... RXF 1 1 RXF RXF = 0 FORWARD RXF = 1 REVERSE 0.09ms 0.05ms 0.02ms 0.18ms 0.09ms 0.05ms 5.8ms 1.45ms 2.9ms Data 1 Data – 15 – CXD2589Q Data 3 Data ...
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... CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing Processing Application 1 Anti-rolling is enhanced. Sync window protection is enhanced. – 16 – CXD2589Q Data KSL3 KSL2 KSL1 KSL0 See the $BX commands. ...
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... Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. – 17 – CXD2589Q 1 , and the output is 1 and the output is 1 and the output is 1 and the output is 1/8 ...
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... CXD2589Q ...
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... OPSL1 Data 2 D0 and subsequent data are DF/DAC function settings. Data 2 Data 000 SYCOF 1 MCSL OPSL1 Processing Processing Processing Processing – 19 – CXD2589Q Data ZDPL ZMUT — Data — — — ...
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... Data EMPH SMUT OPSL2 Data 4 Data AD5 AD4 AD3 AD2 AD1 – 20 – CXD2589Q Data Data AD0 — — — Data Data AD0 FMUT LRWO BSBST BBSL D0 — ...
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... Processing Processing Meaning Processing Processing Meaning The attenuation data (AD9 to AD0) consists of 10bits, and can be set in 1023 different ways. 0dB The audio output from 001h to 3FFh is obtained using the following equation. Audio output = 20 log – – 21 – CXD2589Q Attenuation data [dB] 1024 ...
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... However, synchronization can be forcibly performed by setting LRWO = 1. Command bit BSBST = 1 Bass boost is on. BSBST = 0 Bass boost is off. BSBST can be set when OPSL2 = 1. Command bit BBSL = 1 Bass boost is Max. BBSL = 0 Bass boost is Mid. BBSL can be set when OPSL2 = 1. Meaning Meaning Note) Processing Processing – 22 – CXD2589Q ...
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... CXD2589Q ...
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... C1F1 C1F2 C1 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Command bit CPUSR = 1 XLON pin is high. CPUSR = 0 XLON pin is low. Description C2F1 C2F2 C2 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Processing – 24 – CXD2589Q ...
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... The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Pin No. Command bit MTSL1 MTSL0 Mode description XUGF XPCK GFS MNT1 MNT0 MNT3 RFCK XPCK XROF – 25 – CXD2589Q C2PO C2PO GTOP ...
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... CLVP mode gain setting: GMDP: GMDS Gain Gain GMDP MDP1 MDP0 0 0 –6dB 0 1 0dB 1 0 +6dB Gain Gain Gain MDS1 MDS0 MDP0 Gain CLVS Gain Gain MDS0 MDS1 – 26 – CXD2589Q GMDS –6dB 0dB +6dB ...
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... The rotational velocity R of the spindle can be expressed with the following equation. 256 – Relative velocity at normal speed = 1 n: VP0 to 7 setting value F0 VP0 to 7 setting value [HEX] Fig. 1-1 – 27 – CXD2589Q Data VP3 VP2 VP1 VP0 32 ...
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... CLV CLV CAV CAV-W – 28 – CXD2589Q Data SFSL VC2C HIFC LPWR VPON Description 1 Description Crystal reference CLV servo. Used for normal-speed 2 playback in CLV-W mode. Spindle control with VP0 to 7. Spindle control with the external ...
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... KICK 1 BRAKE STOP KICK 0 BRAKE STOP CAV-W KICK 1 BRAKE STOP Mode LPWR CLV CLV 1-10 (EPWM = 0) 1 1-11 (EPWM = 0) CAV-W 0 1-12 (EPWM = 1) 1 1-13 (EPWM = CAV-W mode. Timing chart 1-2 (a) 1-2 (b) 1-2 (c) 1-3 (a) 1-3 (b) 1-3 (c) 1-4 (a) 1-4 (b) 1-4 (c) 1-5 (a) 1-5 (b) 1-5 (c) 1-6 (a) 1-6 (b) 1-6 (c) Timing chart 1-7 1-8 1-9 – 29 – CXD2589Q ...
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... KICK H MDP (a) KICK BRAKE Z MDP L (b) BRAKE BRAKE Z MDP L (b) BRAKE BRAKE Z MDP (b) BRAKE BRAKE MDP L (b) BRAKE BRAKE MDP Z (b) BRAKE – 30 – CXD2589Q STOP Z MDP (c) STOP STOP Z MDP (c) STOP STOP Z MDP (c) STOP STOP Z MDP (c) STOP STOP MDP Z (c) STOP ...
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... CAV-W mode EPWM = LPWR = 0 Acceleration MDP 264kHz 3.8µs Timing Chart 1-11 CAV-W mode EPWM = LPWR = 1 Acceleration MDP 264kHz 3.8µs n · 236 (ns The BRAKE pulse is masked when LPWR = 1. The BRAKE pulse is masked when LPWR = 1. – 31 – CXD2589Q Z Deceleration Z Deceleration Z Z Deceleration Z ...
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... Timing Chart 1-12 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L H MDP L Timing Chart 1-13 CAV-W mode EPWM = LPWR = 1 H PWMI MDP Acceleration Acceleration The BRAKE pulse is masked when LPWR = 1. – 32 – CXD2589Q Deceleration ...
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... This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes can be read from SBSO by inputting EXCK to the CXD2589Q. Sub Q can be read out after checking the CRC of the 80bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high ...
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... Timing Chart 2-1 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO S0· Same 400ns max S0 · S0· Same Sub Code P.Q.R.S.T.U.V.W Read Timing – 34 – CXD2589Q ...
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... VF0 the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). Load m – 37 – CXD2589Q ...
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... Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc (excluding DATO, CLKO and XLTO). Note) The capture range for this mode is theoretically up to the signal processing limit. – 38 – CXD2589Q ...
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... Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode CLV-W Mode CLV-W CLVP CLV-W MODE START KICK $E8000 Mute OFF $A0XXXXX CAV-W $E6650 (CLVA) NO ALOCK = H ? YES CLV-W $E60C0 (CLVA) (WFCK PLL) YES ALOCK = Fig. 3-2. CLV-W Mode Flow Chart – 39 – CXD2589Q Operation mode Spindle mode Time ...
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... EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2589Q has a built-in three-stage PLL. • The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. ...
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... X'tal XTSL 2/1 MUX Digital PLL Spindle rotation information 1/2 1/32 1/2 1/n Microcomputer 256 control (VP7 to 0) VCOSEL2 1/K VCO2 (KSL1, 0) VPON 1/M 1/N 1/K VCO1 (KSL3, 2) VCOSEL1 RFPLL CXD2589Q – 41 – CXD2589Q CLV-W CAV-W VPCO CLV-N CLV-W CAV-W /CLV-N LPF VCTL V16M VCKI PCO FILI FILO CLTV ...
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... For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. • The CXD2589Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. • The correction status can be monitored externally. ...
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... MNT3 C1 correction MNT1 MNT0 4-4. DA Interface • The CXD2589Q DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. C2 correction Strobe – 43 – CXD2589Q ...
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... There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2589Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit the channel status ...
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... DATO CLKO XLTO Fig. 4-2. Auto focus Focus search up FOK = H NO YES (Checks whether FZC is continuously high for the period of time E set with register 5) FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 4-3-(a). Auto Focus Flow Chart – 46 – CXD2589Q Micro-computer ...
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... Fig. 4-7. N can be set to 216 tracks. CNIN is used for counting the number of jumps. This N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. Blind E Fig. 4-3-(b). Auto Focus Timing Chart – 47 – CXD2589Q $08 ...
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... REV jump) sled servo OFF WAIT (Blind A) CNIN = NO YES Track REV (FWD kick for REV jump) kick WAIT (Brake B) Track, sled servo ON END Fig. 4-4-(a). 1-Track Jump Flow Chart $2C ($28) Fig. 4-4-(b). 1-Track Jump Timing Chart – 48 – CXD2589Q Brake B $25 ...
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... Track, sled FWD kick WAIT (Counts CNIN (Blind A) CNIN = YES Track, REV kick C = Overflow ? (Checks whether the CNIN cycle NO is longer than overflow C) YES Track, sled servo ON END Fig. 4-5-(a). 10-Track Jump Flow Chart CNIN 5 count $2E ($2B) – 49 – CXD2589Q 5) Overflow C $25 ...
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... Command for SSP $2A ($2F) Fig. 4-6-(b). 2N-Track Jump Timing Chart 2N Track Track, sled FWD kick WAIT (Blind A) CNIN = N NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END CNIN Overflow N count $2E ($2B) $26 ($27) – 50 – CXD2589Q Kick D $25 ...
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... Fig. 4-7-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLT CNIN BUSY Blind A $22 ($23) Command for SSP Fig. 4-7-(b). N-Track Move Timing Chart N Track move Track servo OFF Sled FWD kick WAIT (Blind A) CNIN = N NO YES Track, sled servo OFF END END CNIN N count – 51 – CXD2589Q $20 ...
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... MDS Error Measure 2/1 MUX Gain MDS MUX CLV P/S Over Sampling Filter-2 Noise Shape Modulation PWMI Mode Select LPWR MDP Spindle drive signal from the microcomputer for CAV servo Fig. 4-8. Block Diagram – 52 – CXD2589Q MDP Error Measure Over Sampling Filter-1 Gain MDP 1/2 ...
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... Asymmetry Compensation BIAS Fig. 4-9. Example of Asymmetry Compensation Application Circuit CXD2589Q ASYO ASYI – 53 – CXD2589Q ...
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... DAC Block Input Timing Timing Chart 5-1 shows the input timing for the DAC block. Audio data is not transferred from the CD signal processer block to the DAC block inside the CXD2589Q. This is to allow data to be sent to the DAC block via the audio DSP, etc. ...
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... When setting FMUT, set OPSL2 to 1. (See the $AX commands.) Zero detection mute Forced mute is applied when the $9X command ZMUT is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) Soft mute on 23.2 [ms] – 55 – CXD2589Q Soft mute off 23.2 [ms] ...
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... Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 5-2 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 –14. 100 300 1k 3k Digital Bass Boost Frequency Response [Hz] Graph 5-2. – 57 – CXD2589Q Normal DBB MID DBB MAX 10k 30k ...
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... LPF Block The CXD2589Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency determined flexibly. The reference voltage ( ( The LPF block application circuit is shown below. ...
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... Setting Method of the CXD2589Q Playback Speed (in CLV-N mode) (A) CD-DSP block The playback modes shown below can be selected by the combination of the crystal, XTSL pin and DSPB command of $9X. CD-DSP block playback speed X'tal XTSL DSPB 768Fs 1 768Fs 1 384Fs 0 384Fs 0 384Fs 44.1kHz 1 Low power consumption mode ...
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... SONY CODE QFP-80P-L03 EIAJ CODE LQFP080-P-1414 JEDEC CODE 80PIN QFP (PLASTIC 0.15 0.3 – 0.1 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 61 – CXD2589Q + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 0.1 + 0.15 0.1 – 0.1 0° to 10° EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g ...