cxd2589q Sony Electronics, cxd2589q Datasheet - Page 6

• Manufacturer Part Number: cxd2589q
• Description: Cd Digital Signal Processor
• Manufacturer: Sony Electronics

Notes) • PCMD is an MSB first, two's complement output.
Pin
No.
72
73
74
75
76
77
78
79
80
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed).
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
XV
AV
LOUT2
AIN2
AOUT2
AV
AV
XRST
V
Symbol
sync protection.
and the EFM signal transition point coincide.
DD
SS
SS
DD
SS
—
—
—
—
O
O
I
I
I/O
—
—
—
—
GND for master clock.
Analog GND.
Right-channel LINE output.
Right-channel operational amplifier input.
Right-channel analog output.
Analog power supply (+5V).
Analog GND.
System reset. Reset when low.
Power supply (+5V).
– 6 –
Description
CXD2589Q