ade3700 STMicroelectronics, ade3700 Datasheet
ade3700
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ade3700 Summary of contents
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... ICs, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for analog-only input LCD display applications. The ADE3700 covers the full range of XGA and SXGA analog-only applications including Smart Panel designs. The ADE3700 family is pin-to-pin compatible and comes in a low-cost, 128-pin LQFP package ...
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... Per pin delay 6ns in 0.4ns increments Adaptive Slew Rate control outputs Differential clock Spread spectrum -programmable digital FM modulation of the output clock with no external components Output Format Supports resolutions up to SXGA @ 75Hz Supports 6- or 8-bit Panels Supports double or single pixel wide formats ADE3700 ...
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... ADE3700 Chapter 1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 Pin Descriptions .................................................................................................................. 7 Chapter 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1 Global Control .................................................................................................................... 11 2.2 FM Frequency Synthesizer ................................................................................................ 16 2.3 Analog-to-Digital Converter (ADC) ..................................................................................... 17 2.4 Line Lock PLL .................................................................................................................... 18 2.5 Sync Retiming (SRT) ......................................................................................................... 23 2.6 Sync Measurement ............................................................................................................ 25 2.7 Sync Multiplexer (SMUX) ................................................................................................... 32 2.7.1 Functional Description .......................................................................................................................33 2.7.2 Example .............................................................................................................................................34 2.8 Data Multiplexer ................................................................................................................. 37 2.9 Data Measurement (DMEAS) ............................................................................................ 38 2.9.1 Edge Intensity ....................................................................................................................................38 2.9.2 Pixel Sum ...........................................................................................................................................38 2 ...
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... Absolute Maximum Ratings ................................................................................................84 3.2 Power Consumption Matrices .............................................................................................84 3.3 Nominal Operating Conditions ............................................................................................85 3.4 Preliminary Thermal Data ...................................................................................................85 3.5 Preliminary DC Specifications ............................................................................................85 3.5.1 LVTTL 5 Volt Tolerant Inputs With Hysteresis ................................................................................... 85 3.5.2 LVTTL 5 Volt Tolerant Inputs ............................................................................................................. 85 3.5.3 LVTTL 5 Volt Tolerant I/O With Hysteresis ........................................................................................ 86 3.5.4 LVTTL Outputs .................................................................................................................................. 86 3.6 Preliminary AC Specifications ...........................................................................................86 Chapter 4 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Chapter 5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4/89 ADE3700 ...
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... Initialize The MCU typically programs the ADE3700 with a number of default values and sets up the ADE3700 to identify activity on any of the input pins. All pre- configured values and RAMs, such as DVI settings, line-lock PLL settings, OSD characters, LCD timing values (output sequencer), scale kernels, gamma curves, sRGB color warp, APC dithering, output pin configuration (OMUX), etc ...
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... When the MCU calls for an autotune, the MCU sets up an iterative loop to search for the best phase, gain, offset, etc. At each step of the loop, the MCU kicks off a test in which the ADE3700 which performs extensive statistical analysis of the incoming data stream. The results of the analysis are made available to the MCU which is responsible for the optimization algorithm ...
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... ADE3700 1.1 Pin Descriptions LQFP128 Name 32 XVDD18 31 XTAL_OUT 30 XTAL_IN 29 XGND 19 XCLK_EN 18 XCLK 34 VSYNC 21 TSTCLK 65 TST_SCAN 8 TCON7 9 TCON6/OVS 10 TCON5/OHS 11 TCON4/ODE 12 TCON3 13 TCON2 14 TCON1 15 TCON0 17 SDA 16 SCL 20 RESETN 54 REFR 55 REFMR 48 REFMG 41 REFMB 47 REFG 58 REFCR 51 REFCG 44 REFCB 40 REFB 26 PVDD18 28 PVDD18 25 PGND 27 PGND 105 AVS 126 ...
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... Output Port A: Green Data 2 Output Output Port A: Green Data 1 Output Output Port A: Green Data 0 Output Alternate Data Enable Output Output Clock Input/Output Output Port B: Blue Data 7 Input/Output Output Port B: Blue Data 6 Input/Output Output Port B: Blue Data 5 Input/Output Output Port B: Blue Data 4 ADE3700 Description ...
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... ADE3700 LQFP128 Name 108 OBB3 109 OBB2 110 OBB1 111 OBB0 66 OBA7 67 OBA6 68 OBA5 69 OBA4 70 OBA3 71 OBA2 72 OBA1 73 OBA0 56 INR 49 ING 42 INB 35 HSYNC 7 DVDD33 64 DVDD33 80 DVDD33 91 DVDD33 106 DVDD33 119 DVDD33 23 DVDD18 62 DVDD18 84 DVDD18 93 DVDD18 117 DVDD18 124 DVDD18 6 DGND 22 DGND ...
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... Analog 3.3V VDD Power Analog 3.3V VDD Power Analog 3.3V VDD Power Analog 3.3V VDD Power Analog 1.8V VDD Power Analog 1.8V VDD Power Analog 1.8V VDD Power Analog Ground Power Analog Ground Power Analog Ground Power Analog Ground Power Analog Ground Power Analog Ground Power 1.8V VDD ADE3700 Description ...
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... SCLK Freq. Domain Synthesizer Frequency Range < AND XCLK OUT XCLK < AND XCLK OUT XCLK Global Control ADE3700 Flicker Detection Output TCON FM Freq. DOTCLK Synthesizer Domain , in MHz), the following OUT SDIV 0 1 ORA OGA OBA ...
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... AND XCLK OUT XCLK < AND XCLK OUT XCLK < AND XCLK OUT XCLK < f /16 AND XCLK OUT XCLK (6 + NDIV - SDIV OUT (6 + NDIV - SDIV XCLK (2+NDIV XTAL ADE3700 SDIV OUT ...
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... ADE3700 Register Name GLBL_NULL_ADDR GLBL_CLK_SRC_SEL_0 GLBL_CLK_SRC_SEL_2 Table 4: Global Registers (Sheet Addr. mode Bits Default 0x0000 Read [7:0] 0x0001 [7] 0x0 R/W [6:4] 0x5 R/W [3:0] 0xA 0x0002 [7] 0x0 R/W [6:4] 0x4 [3] R/W [2:0] 0x4 Global Control Description Chip Revision ID Reserved DOTCLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: FM freq synth (normal) ...
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... R/W [4:3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x1 ADE3700 Description Reserved Invert LLPLL control clock Invert LLPLL zero clock Invert ADC sample clock Invert DOT clock Invert input clock Reserved Clock enable async override Reserved Blue ADC power down Green ADC power down Red ADC power down ...
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... ADE3700 Register Name GLBL_SCLK_MD_SD GLBL_SCLK_PE_L GLBL_SCLK_PE_H GLBL_TST_CTRL GLBL_COMP_PAD_CTRL GLBL_SCLK_CTRL GLBL_BPAD_EN GLBL_IK_SRST GLBL_SHADOW_EN Table 4: Global Registers (Sheet Addr. mode Bits Default 0x000A R/W [7:3] 0x0 R/W [2:0] 0x0 0x000B R/W [7:0] 0x0 0x000C R/W [7:0] 0x000D [7:1] 0x0 R/W [0] 0x0 0x000E [7:2] 0x0 R/W [1] 0x0 R/W [0] 0x1 0x0010 [7:5] 0x0 R/W [4] 0x0 [3] 0x0 R/W [2:0] 0x0 0x0011 R/W [3:0] 0x0 ...
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... OUT 27+NDIV phase_rate OUT XCLK ADE3700 Description Reserved Enable DFT clock Enable DMEAS clock Enable INCLK to I2C registers Reserved PGEN block reset synchronous to DOTCLK OMUX block reset synchronous to DOTCLK APC block reset synchronous to DOTCLK ...
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... ADE3700 Table 5: FM Frequency Synthesizer Registers Register Name FM_FS_CTRL FM_FS_PR_0 FM_FS_PR_1 FM_FS_PR_2 FM_FS_PR_3 FM_FS_AMPLITUDE FM_FS_PERIODX64 FM_FS_PULSE_EXT 2.3 Analog-to-Digital Converter (ADC) The analog port consists of three 9-bit RGB ADCs with preamp, gain/offset adjustment and digital filtering. The I2C interface for the ADC block is in the INCLK clock domain which must be active for programming ...
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... Figure 3: Line Lock PLL Error <= LOCK_TOL for more than LOCK_LINE_NB of lines Slow Error > LOCK_TOL Error > SLOW_TOL x SQRT(5 x M_FACTOR / ( ADE3700 Description Offset Control, Blue Channel Gain Control, Red Channel Gain Control, Green Channel Gain Control, Blue Channel Figure 3. Lock BE ...
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... ADE3700 Table 7: Line Lock PLL Registers (Sheet Register Name LLK_PLL_CLEAR LLK_PLL_CTRL LLK_PLL_MFACTOR_L LLK_PLL_MFACTOR_H LLK_PLL_HPERIOD_L LLK_PLL_HPERIOD_H LLK_PLL_PHASE_RATE_INIT_0 LLK_PLL_PHASE_RATE_INIT_1 LLK_PLL_PHASE_RATE_INIT_2 LLK_PLL_PHASE_RATE_INIT_3 LLK_PLL_PHASE_RATE_INIT_WR Addr Mode Bits Default 0x0800 [7:6] R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0801 R/W [7] R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 ...
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... R/W [5:0] 0x20 0x0817 R/W [7:0] 0x80 0x0818 R/W [7:0] 0x10 ADE3700 Description Reserved Fast Time Constant A Exponent Reserved Fast Time Constant B Exponent Reserved Fast Time Constant A Linear Reserved Fast Time Constant B Linear Reserved Slow Time Constant A Exponent Reserved Slow Time Constant B Exponent Reserved ...
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... ADE3700 Table 7: Line Lock PLL Registers (Sheet Register Name LLK_PLL_LOCK_TOL LLK_PLL_LOCK_LINE_NB LLK_PLL_PH_OFFSET LLK_PLL_PH_OFFSET_EN LLK_PLL_PULSE_HIGH_EXT LLK_PLL_STAT_LINES_L LLK_PLL_STAT_LINES_H LLK_PLL_STAT_ERROR_INC_LO W LLK_PLL_FINE_ERROR_WAIT LLK_PLL_STAT_ON_VSYNC LLK_PLL_MFACTOR_SHADOW_L LLK_PLL_MFACTOR_SHADOW_U Addr Mode Bits Default 0x0819 R/W [7:0] 0x20 0x081A R/W [7:0] 0x30 0x081B R/W [7:0] 0x0 0x081C R/W [7] 0x0 [6] [5] [4:0] 0x081D R/W [7] 0x0 [6:3] R/W [2:0] 0x0 0x081E R/W [7:0] 0x10 0x081F ...
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... R [7:0] 0x084E R [7:0] 0x084F R [7:0] 0x0850 R [7:0] 0x0851 [7:0] ADE3700 Description In free-running mode, toggles when status is updated. In one-shot mode, this bit is set when status is ready. Reserved 0: free-running mode 1: one-shot mode update enable Reserved llk overflow coarse error = 0 in slow mode in lock mode phase error LSB = approx ...
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... ADE3700 2.5 Sync Retiming (SRT) The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into the XCLK and INCLK domains. For the XCLK domain, the SRT has the following functions: Retimes all sync signals going to SMEAS into the XCLK domain. ...
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... R/W [1:0] 0x0 0x01F1 [7:2] 0x0 R/W [1:0] 0x0 ADE3700 Description Reserved coast signal trigger edge 0: posedge of selected vertical 1: negedge of selected vertical source select for coast vert sync trigger 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: Reserved 0x4: nc ...
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... ADE3700 2.6 Sync Measurement The Input Sync Measurement (SMEAS) block continuously detects activity from all video sources. The module can measure the characteristics of the sync signals on any input port. The sync measurement module reports the results of the measurements to the system microcontroller. This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming sync signals ...
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... R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 ADE3700 Description timeout counter value for vertical measurement in units of XCLK/256 Reserved clear sticky status bits clear all out-of-range event counters clear all result registers Reserved Enable hsync filter -- all hsync pulses less than SMEAS_FILTER_HS_WIDTH will be ignored. ...
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... ADE3700 Register Name SMEAS_V_CTRL SMEAS_H_SEL Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x0112 [7:5] R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0113 [7:4] R/W [3:0] 0x0 Sync Measurement Description Reserved Enable Vertical Measurement in Free- running mode Vertical Event Edge Select 0: positive edge 1: negative edge Freeze vertical measurement results during free-running mode ...
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... R/W [0] 0x0 0x011A R/W [7:0] 0x0 0x011B R/W [7:0] 0x0 ADE3700 Description Selects a vertical signal for measurement of the high pulse width. 0x0: Analog vsync 0x1: Composite vsync 0x2: SOG vsync 0x3: nc 0x4: nc 0x5: nc 0x6: nc 0x7: TCON vsync 0x8 - 0xF: Reserved Selects a vertical signal for measurement of period and polarity ...
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... ADE3700 Register Name SMEAS_H_SKIP_H SMEAS_SKEW_CTRL SMEAS_SKEW_THRES SMEAS_DELAY_VSYNC SMEAS_REF_XK_PER_H_L SMEAS_REF_XK_PER_H_M SMEAS_REF_XK_PER_H_H SMEAS_REF_XK_PER_V_L SMEAS_REF_XK_PER_V_M SMEAS_REF_XK_PER_V_H SMEAS_REF_H_PER_V_L SMEAS_REF_H_PER_V_H SMEAS_REF_XK_V_PER_HI_L SMEAS_REF_XK_V_PER_HI_M SMEAS_REF_XK_V_PER_HI_H SMEAS_REF_POLARITY SMEAS_XK_HTOL_EXP SMEAS_XK_VTOL_EXP Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x011C R/W [7:4] [3:0] 0x011D [7:3] 0x0 R/W [2] 0x0 [1] 0x0 R/W [0] 0x0 0x011E R [7:0] 0x5 0x011F R/W [7:0] 0x3 0x0120 ...
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... R [7:0] 0x0 0x0151 [7:2] 0x0 R [1] 0x0 R [0] 0x0 ADE3700 Description Reserved n Horizontal per vertical tolerance, ± 2 Refer to register 0x0111 Reserved Toggle on activity status update in free- running mode. No function in one-shot mode. Reserved Composite sync is active Vsync from SOG separator is active Comp vsync from composite sync separator ...
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... ADE3700 Register Name SMEAS_STATUS_RANGE SMEAS_MEAS_POLLING SMEAS_SKEW_STATUS Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x0152 R [7] 0x0 R [6] 0x0 R [5] 0x0 R [4] 0x0 R [3] 0x0 R [2] 0x0 R [1] 0x0 R [0] 0x0 0x0153 [7:2] 0x0 R [1] 0x0 R [0] 0x0 0x0154 [7:2] 0x0 R [1] ...
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... Signal Generator H/V Reference hcount Signals vcount ADE3700 Description The number of times the XCLKs per vertical reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the XCLKs per horizontal reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1] ...
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... ADE3700 2.7.1 Functional Description The internal signal selector selects which of the input sources are to be used for the internal hsync, vsync and enab signals and is controlled by I2C register SMUX_CTRL0. The signal generator contains a horizontal and a vertical counter that are resynced using a horizontal and vertical reference signals respectively. The selection of the H/V references and the resync edge (either rising or falling) are programmed via SMUX_CTRL1[3:0] ...
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... Addr Mode Bits Default [7:6] 0x0 R/W [5:3] 0x0 R/W [2:0] 0x0 ADE3700 Description Reserved Vsync_internal select 0x0 = Reserved 0x1 = llk/VGA vsync 0x2 = Reserved 0x3 = composite sync decoder 0x4 = Reserved Hsync_internal select 0x0 = Reserved 0x1 = llk synthesized hsync 0x2 = Reserved 0x3 = raw VGA hsync (jitter) ...
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... ADE3700 Table 11: Sync Multiplexer Registers (Sheet Register Name SMUX_CTRL1 0x0201 SMUX_CTRL2 0x0202 Addr Mode Bits Default R/W [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 R [7] 0x0 R/W [6] 0x0 R/W [5:4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 Sync Multiplexer (SMUX) Description venab out select 0: derived from enab out ...
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... R/W [7:0] 0x00 R/W [3:0] 0x0 R/W [7:0] 0x00 R/W [3:0] 0x0 ADE3700 Description venab pending state 0x0: idle 0x1: venab pending frame 1 0x2: venab pending frame 2 Wait until 0 to write venab again if in henab or venab shadow mode. henab pending Reserved vtrigger reference 2’bx0: trigger ref = venab 2’b01: last pixel w/ anti-glitch 2’ ...
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... ADE3700 Table 11: Sync Multiplexer Registers (Sheet Register Name HSYNC_PHASE 0x0210 VSYNC_PHASE 0x0211 HENAB_SET_HW_L 0x0212 HENAB _SET_HW _U 0x0213 HENAB _RST_HW _L 0x0214 HENAB _RST_HW _U 0x0215 VENAB_SET_HW _L 0x0216 VENAB _SET_HW _U 0x0217 VENAB _RST_HW _L 0x0218 VENAB _RST_HW _U 0x0219 2.8 Data Multiplexer The Data Multiplexer provides the following functions: Debug modes (e ...
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... Delta_val on Blue channel 2.9.2 Pixel Sum The Pixel Sum is the sum of all selected pixels for either a specific color channel or all color channels within the window specified. 2.9.3 Minimum/Maximum Pixel This function reports the minimum and maximum pixel found within the specified window. 38/89 ADE3700 ...
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... ADE3700 2.9.4 Pixel Cumulative Distribution (PCD) The Pixel Cumulative Distribution (PCD) function reports the total number of pixels greater than (or less than) a programmable threshold. To switch between pixels greater than or pixels less than the threshold, a control bit is provided in the DMM_Mode register when requesting a measurement. ...
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... Addr Mode Bits Default 0x0900 [7:6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1:0] 0x0 ADE3700 ALG_SEL = 10 ALG_SEL = 11 HPOS_MIN [7:0] DE_SIZE_OUT [7:0] HPOS_MIN [11:8] DE_SIZE_OUT [15:8] HPOS_MAX [7:0] DE_MISMATCH_FLAG HPOS_MAX [11:8] 8’h00 VPOS_MIN [7:0] 8’h00 VPOS_MIN [11:8] 8’h00 VPOS_MAX [7:0] 8’h00 VPOS_MAX [11:8] 8’h00 Description color select 00: all 01: red 10: green 11: blue vsync edge select ...
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... ADE3700 Table 14: Data Measurement Registers (Sheet Register Name DMEAS_MODE_CTRL DMEAS_THRESHOLD DMEAS_WIN_MIN_X_L DMEAS_WIN_MIN_X_H DMEAS_WIN_MAX_X_L DMEAS_WIN_MAX_X_H DMEAS_WIN_MIN_Y_L DMEAS_WIN_MIN_Y_H DMEAS_WIN_MAX_Y_L DMEAS_WIN_MAX_Y_H DMEAS_DE_REF_L DMEAS_DE_REF_L DMEAS_DE_TOL DMEAS_DATA_0 DMEAS_DATA_1 DMEAS_DATA_2 DMEAS_DATA_3 DMEAS_DATA_4 DMEAS_DATA_5 DMEAS_DATA_6 DMEAS_DATA_7 Addr Mode Bits Default 0x0901 R/W [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [1] 0x0 ...
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... R/W [7:0] 0x0 0x0A07 R/W [0] 0x0 0x0A08 R/W [7:0] 0x0 0x0A09 R/W [7:0] 0x0 ADE3700 Description Scratch Pad Registers Description Input Horizontal Resolution Bits [3:0] must be set to zero. Input Vertical Resolution Bits[3:0] must be set to 0. 17-bit Horizontal Scale Factor = (in_hpixel << 16) / dest_hpixel + 0.5 16-bit Vertical Scale Factor = (in_vpixel << 15) / dest_vpixel + 0.5 ...
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... ADE3700 Register Name SCL_ORIGHPOS_0 SCL_ORIGHPOS_1 SCL_ORIGHPOS_2 SCL_ORIGHPOS_3 SCL_ORIGVPOS_E_0 SCL_ORIGVPOS_E_1 SCL_ORIGVPOS_E_2 SCL_ORIGVPOS_E_3 SCL_THRES_SLOPE SCL_THRES_OFFSET_L SCL_THRES_OFFSET_H SCL_CBBYPASS SCL_CON_CAL_SEL SCL_TESTCON SCL_LUT1 SCL_LUT2 SCL_LUT3 SCL_LUT4 SCL_LUT5 SCL_LUT6 Table 15: LCD Scaler Registers (Sheet Addr Mode Bits Default 0x0A0A R/W [7:0] 0x0 0x0A0B R/W [7:0] 0x0 0x0A0C R/W [7:0] 0x0 0x0A0D RW [2:0] ...
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... R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 ADE3700 Description Sigmoidal Function LUT Entry 7, 8-bit 2’s complement Sigmoidal Function LUT Entry 8, 8-bit 2’s complement Sigmoidal Function LUT Entry 9, 8-bit 2’s complement Sigmoidal Function LUT Entry 10, 8-bit 2’s complement Sigmoidal Function LUT Entry 11, 8-bit 2’s complement Sigmoidal Function LUT Entry 12, 8-bit 2’ ...
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... ADE3700 2.11 Output Sequencer The Output Sequencer module synchronizes timing for the output video interface. It allows sufficient flexibility to support a broad range of Smart Panel applications as well using the Output Timing Controller (TCON) module, refer to horizontal and vertical counters, which are locked with the input video stream. ...
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... R/W [7:0] 0x0 0x0BCA R/W [7:0] 0x0 0x0BCB [7:4] R/W [3:0] 0x0 ADE3700 Description OUT_VMAX detected, sticky bit OUT_VMAX detect reset Interlace Enable Fractional Line Extend Frame Lock Reference 0: Last Input Pixel 1: First Input Pixel Frame Lock Selection 0: Last Line Variable 1: Fixed Line Length ...
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... ADE3700 Table 16: Output Sequencer Registers (Sheet Register Name OSQ_VERTEN_DLY_O_L OSQ_VERTEN_DLY_O_M OSQ_VERTEN_DLY_O_H OSQ_VSYNC_SET_L OSQ_VSYNC_SET_H OSQ_VSYNC_RST_L OSQ_VSYNC_RST_H OSQ_HSYNC_SET_L OSQ_HSYNC_SET_H OSQ_HSYNC_RST_L OSQ_HSYNC_RST_H OSQ_HENAB_SET_L OSQ_HENAB_SET_H OSQ_HENAB_RST_L OSQ_HENAB_RST_H OSQ_VENAB_SET_L OSQ_VENAB_SET_H OSQ_VENAB_RST_L OSQ_VENAB_RST_H OSQ_OUT_VCOUNT Addr Mode Bits Default 0x0BCC R/W [7:0] 0x0 0x0BCD R/W [7:0] 0x0 0x0BCE [7:4] 0x0 R/W [3:0] 0x0 0x0BCF ...
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... R/W [7:0] 0x0 0x0B22 R/W [7:0] 0x0 0x0B23 R/W [7:0] 0x0 ADE3700 Description Reserved 0: no TCON pipe delay matching 1: TCON pipe delay enabled (normal) Initialize SRTDs Enable TCON count comparison value [7:0] Reserved 0: horizontal count compare 1: vertical count compare count comparison value [11:8] Refer to TCON_COMP_0 for definition ...
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... ADE3700 Register Name TCON_COMP_10_L TCON_COMP_10_H TCON_COMP_11_L TCON_COMP_11_H TCON_COMP_12_L TCON_COMP_12_H TCON_COMP_13_L TCON_COMP_13_H TCON_COMP_14_L TCON_COMP_14_H TCON_COMP_15_L TCON_COMP_15_H TCON_COMP_16_L TCON_COMP_16_H TCON_COMP_17_L TCON_COMP_17_H TCON_COMP_18_L TCON_COMP_18_H TCON_COMP_19_L TCON_COMP_19_H TCON_COMP_20_L TCON_COMP_20_H TCON_COMP_21_L TCON_COMP_21_H TCON_COMP_22_L TCON_COMP_22_H TCON_COMP_23_L TCON_COMP_23_H TCON_COMP_24_L TCON_COMP_24_H TCON_COMP_25_L TCON_COMP_25_H TCON_COMP_26_L TCON_COMP_26_H Table 17: TCON Registers (Sheet Addr ...
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... R/W [7:0] 0x0 0x0B68 R/W [7:0] 0x0 0x0B69 R/W [7:0] 0x0 ADE3700 Description Refer to TCON_COMP_0 for definition Reserved SRTD initialization state 0x0: f (A&B,&C&D,0,0) 0x1: f (A&B,&C&D,0,0) 0x2: f (A&B,&C&D,0,0) 0x3: f (0,0,A&B,0) 0x4: f (0,0,0,A&B) 0x5: f (0,0,0,A|B) 0x6: f (0,0,0,A^B) 0x7: f (0,0,0,!(A&B)) where f(Set, Reset, Toggle, Dflop programmable logic/flop element Refer to TCON_SRTD_0 for definition ...
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... ADE3700 Register Name TCON_SRTD_26 TCON_SRTD_27 TCON_SRTD_28 TCON_SRTD_29 TCON_SRTD_30 TCON_SRTD_31 TCON_X_0 TCON_X_1 TCON_X_2 TCON_X_3 TCON_X_4 TCON_X_5 TCON_X_6 TCON_X_7 TCON_X_8 TCON_X_9 TCON_X_10 TCON_X_11 TCON_X_12 TCON_X_13 TCON_X_14 TCON_X_15 TCON_X_16 TCON_X_17 Table 17: TCON Registers (Sheet Addr. Mode Bits Default 0x0B6A R/W [7:0] 0x0 0x0B6B R/W [7:0] 0x0 0x0B6C ...
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... R/W [7:0] 0x0 0x0BA5 R/W [7:0] 0x0 0x0BA6 R/W [7:0] 0x0 0x0BA7 R/W [7:0] 0x0 ADE3700 Description input selection for SRTD_9.A (Refer to Table 18 for definition) input selection for SRTD_9.B (Refer to Table 18 for definition) input selection for SRTD_10.A (Refer to Table 18 for definition) input selection for SRTD_10.B (Refer to Table 18 for definition) input selection for SRTD_11 ...
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... ADE3700 Register Name TCON_X_40 TCON_X_41 TCON_X_42 TCON_X_43 TCON_X_44 TCON_X_45 TCON_X_46 TCON_X_47 TCON_X_48 TCON_X_49 TCON_X_50 TCON_X_51 TCON_X_52 TCON_X_53 TCON_X_54 TCON_X_55 TCON_X_56 TCON_X_57 TCON_X_58 TCON_X_59 TCON_X_60 TCON_X_61 Table 17: TCON Registers (Sheet Addr. Mode Bits Default 0x0BA8 R/W [7:0] 0x0 0x0BA9 R/W [7:0] 0x0 0x0BAA R/W [7:0] 0x0 0x0BAB ...
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... R/W [7:0] 0x0 Table 18: Input Selection Values Value 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F ADE3700 Description input selection for SRTD_31.A (Refer to Table 18 for definition) input selection for SRTD_31.B (Refer to Table 18 for definition) Description 2 frame + 2 line + 1 pixel toggle HCOUNT[0] HCOUNT[1] VCOUNT[0] ...
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... ADE3700 When the programmed block size is such that the complete 8x8 grid is smaller than the total screen area, the part of the screen area which is outside the 8x8 grid is forced to black. 2.13.2 Pattern Engine In order to display two patterns simultaneously on the LCD screen, the Pattern Generator has two pattern display engines ...
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... R/W [7:0] 0x0 0x0614 [7:4] R/W [3:0] 0x0 0x0615 R/W [7:0] 0x0 ADE3700 Description Grid Row 3 Grid Row 4 Grid Row 5 Grid Row 6 Grid Row 7 width of a grid block in pixels [7:0] Reserved width of a grid block in pixels [11:8] height of a grid block in pixels [7:0] Reserved height of a grid block in pixels [11:8] grid block horizontal offset in pixels [7:0] ...
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... ADE3700 Register Name PGEN_P0_WIDTH_X_OFFSET_H PGEN_P0_HEIGHT_Y_L PGEN_P0_HEIGHT_Y_H PGEN_P0_HEIGHT_Y_OFFSET_L PGEN_P0_HEIGHT_Y_OFFSET_H PGEN_P1_WIDTH_X_L PGEN_P1_WIDTH_X_H PGEN_P1_WIDTH_X_OFFSET_L PGEN_P1_WIDTH_X_OFFSET_H PGEN_P1_HEIGHT_Y_L PGEN_P1_HEIGHT_Y_H PGEN_P1_HEIGHT_Y_OFFSET_L PGEN_P1_HEIGHT_Y_OFFSET_H PGEN_P0_COLOR_R_C0 PGEN_P0_COLOR_G_C0 PGEN_P0_COLOR_B_C0 PGEN_P0_COLOR_R_C1 PGEN_P0_COLOR_G_C1 PGEN_P0_COLOR_B_C1 PGEN_P1_COLOR_R_C0 PGEN_P1_COLOR_G_C0 PGEN_P1_COLOR_B_C0 PGEN_P1_COLOR_R_C1 PGEN_P1_COLOR_G_C1 PGEN_P1_COLOR_B_C1 PGEN_P0_GRADDELTA_R PGEN_P0_GRADDELTA_G PGEN_P0_GRADDELTA_B Table 19: PGEN Registers (Sheet Addr Mode Bits Default 0x0616 ...
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... R/W [2:0] 0x0 0x063F [7] R/W [6:4] 0x0 [3] R/W [2:0] 0x0 ADE3700 Description Pattern 0 Gradient Horizontal Step Pattern 0 Gradient Vertical Step Pattern 1 Gradient Delta On Red Pattern 1 Gradient Delta On Green Pattern 1 Gradient Delta On Blue Pattern 1 Gradient Horizontal Step Pattern 1 Gradient Vertical Step Reserved Pattern 0 Bar 1 Color Reserved Pattern 0 Bar 0 Color ...
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... ADE3700 Register Name PGEN_P1_SEQ_COL6_COL7 PGEN_B_TOP_BOTTOM PGEN_B_LEFT_RIGHT PGEN_X_TOTAL_L PGEN_X_TOTAL_H PGEN_Y_TOTAL_L PGEN_Y_TOTAL_H Table 19: PGEN Registers (Sheet Addr Mode Bits Default 0x0640 [7] R/W [6:4] 0x0 [3] R/W [2:0] 0x0 0x0641 R/W [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0642 R/W [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0643 ...
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... R/W [7:6] 0x0 R/W [5:4] 0x0 R/W [3:2] 0x0 R/W [1:0] 0x0 0x0D01 R/W [7:0] 0x0 ADE3700 Description Reserved gamma_b control 0x0: disable 0x1: full screen 0x2: windowed 0x3: Reserved gamma_a control 0x0: disable 0x1: full screen 0x2: windowed 0x3: Reserved sRGB control 0x0: disabled 0x1: full screen 0x2: windowed ...
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... ADE3700 Register Name SRGB_BLACK_G SRGB_BLACK_B SRGB_RED_R SRGB_RED_G SRGB_RED_B SRGB_GREEN_R SRGB_GREEN_G SRGB_GREEN_B SRGB_BLUE_R SRGB_BLUE_G SRGB_BLUE_B SRGB_YELLOW_R SRGB_YELLOW_G SRGB_YELLOW_B SRGB_CYAN_R SRGB_CYAN_G SRGB_CYAN_B SRGB_MAGENTA_R SRGB_MAGENTA_G SRGB_MAGENTA_B SRGB_WHITE_R SRGB_WHITE_G SRGB_WHITE_B SRGB_GAMMA_A_RED_A SRGB_GAMMA_A_RED_B SRGB_GAMMA_A_RED_C SRGB_GAMMA_A_GREEN_A SRGB_GAMMA_A_GREEN_B SRGB_GAMMA_A_GREEN_C SRGB_GAMMA_A_BLUE_A SRGB_GAMMA_A_BLUE_B SRGB_GAMMA_A_BLUE_C SRGB_GAMMA_B_RED_A SRGB_GAMMA_B_RED_B SRGB_GAMMA_B_RED_C Table 20: sRGB Registers (Sheet ...
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... The next byte contains the data to be written to that register. Subsequent bytes are written to successive internal OSD registers. 3. Continue writing data bytes until the desired range of OSD internal registers has been written (the ADE3700 device will issue an ACK on each transfer). 4. Issue an I2C stop sequence. 62/89 ...
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... ADE3700 Character Display There are two 96-character monochrome fonts and two 32-character four-bit color fonts, a total of 256 characters. The four bits of color are an index into one of two 16 entry color lookup tables. Entries in the color lookup table specify a 24-bit RGB color. All fonts and the color look-up table are RAM-based and must be downloaded to the OSD’ ...
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... Addressing is by row and column in the case of character or attribute transfers, and by character index in the case of font transfers. When writing to the color table, the “column” field determines the color table and R/G/B selection. 64/89 ADE3700 ...
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... ADE3700 Header Byte Bits Description First [7:4] Type of data transfer. Valid values are: 0x8: screen map 0x9: color LUT 0xA: attribute map 0xC: font data all others: Reserved [3:0] For screen map or attribute map access, this is the row index. For color LUT access, this is the color index. ...
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... Window 1 Row Start [3:0] Window 1 Row End [7:4] Window 2 Row Start [3:0] Window 2 Row End [7:4] Window 3 Row Start [3:0] Window 3 Row End [7:3] Window 0 Column Start [2] Window 0 Visibility 0: Off 1: On [1] Reserved [0] Window 0 Shadow Enable [7:3] Window 1 Column Start [2] Window 1 Visibility 0: Off 1: On [1] Reserved [0] Window 1 Shadow Enable ADE3700 ...
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... ADE3700 Table 22: OSD Attribute Map Definition (Sheet Row Column Bits Description [7:3] Window 2 Column Start [2] Window 2 Visibility 0: Off 1: On [1] Reserved [0] Window 2 Shadow Enable [7:3] Window 3 Column Start [2] Window 3 Visibility 0: Off 1: On [1] Reserved [0] Window 3 Shadow Enable ...
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... LSBs of background color for 1bpp chars no function for 4bpp color chars [4] blink enable [3:0] foreground color for 1bpp chars for 4bpp color chars [3:2]: Reserved [1]: flip vertical [0]: flip horizontal Table 23: OSD Register Default Addr Mode Bits (hex) 0x0C02 R/W [7:0] 0 ADE3700 Description Description OSD Access Port ...
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... ADE3700 Refer to the Flicker Programming Guide for more details. Register Name FLK_CTRL FLK_HBLOCK_SIZE FLK_FRAME_CNT_MAX FLK_MEAS0_0 FLK_MEAS0_1 FLK_MEAS0_2 FLK_MEAS0_3 FLK_MEAS1_0 FLK_MEAS1_1 FLK_MEAS1_2 FLK_MEAS1_3 FLK_MEAS2_0 FLK_MEAS2_1 FLK_MEAS2_2 Table 24: Flicker Registers (Sheet Addr Mode Bits Default 0x0CA1 R/W [7:6] 0x0 R/W [5] 0x1 R/W [4] 0x0 R/W [2:0] 0x5 0x0CA2 R/W [7:4] 0x0 ...
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... R/W [7:0] 0x0CBF R/W [7:0] 0x0CC0 R/W [7:0] 0x0CC1 R/W [7:0] 0x0 0x0CC2 R/W [7:0] 0x0CC3 R/W [7:0] 0x0CC4 R/W [7:0] 0x0CC5 R/W [7:0] 0x0 0x0CC6 R/W [7:0] 0x0CC7 R/W [7:0] 0x0CC8 R/W [7:0] 0x0CC9 R/W [7:0] 0x0 0x0CCA R/W [7:0] 0x0CCB R/W [7:0] 0x0CCC R/W [7:0] 0x0CCD R/W [7:0] 0x0 0x0CCE R/W [7:0] 0x0CCF R/W [7:0] 0x0CD0 R/W [7:0] ADE3700 Description Score for Pattern 3 Score for Pattern 4 Score for Pattern 5 Score for Pattern 6 Score for Pattern 7 ...
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... ADE3700 Register Name GAMMA_CTRL 2.18 APC APC (formerly known as Arithmos Perfect Color) dithers an input 10 bit video stream down to 4-8 output bits. The dithering is done in space and time in such a way that the eye does not perceive objectionable artifacts such as: Fixed dither patterns Contours Flickering pixels Phase correlated flickering, which creates wave patterns known as “ ...
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... Figure 10: Output Mux Block Diagram 8 8 Byte Flip Red & 24 Blue 8 8 Byte Swap Flip 8 8 Byte Flip tci[13:0] tcon_out[7:0] ADE3700 Figure 10. Single to Data 48 Double Wide Inversion Converter 48 hclk rda[7:0] inv_a gda[7:0] inv_b bda[7:0] rdb[7:0] gdb[7:0] bdb[7:0] Output Mux/Reg FLOPS ...
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... ADE3700 2.19.1 Sub Block Function 2.19.1.1 Right Shift shifts right from positions, fills from the top with zeroes out_mux_ctrl1[2:0] 2.19.1.2 Byte Flip flips data bits in a byte from LSB to MSB, i.e. out[7:0] = in[0:7] out_mux_ctrl0[4] 2.19.1.3 Red & Blue Swap swaps red and blue channels, i.e. out[23:0] = {in[7:0],in[15:8],in[23:16]} out_mux_ctrl0[3] 2 ...
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... RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 0 0 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 0 0 RDA3 RDA3 RDA3 RDA3 RDA3 TCI11 RDA3 RDA3 0 0 RDA2 RDA2 RDA2 RDA2 RDA2 TCI10 RDA2 RDA2 0 0 RDA1 PWMA RDA1 RDA1 RDA1 ADE3700 ...
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... ADE3700 Table 27: Output Mux Specification (Sheet ORA0 OBB7 OBB6 OBB5 OBB4 OBB3 OBB2 OBB1 OBB0 OGB7 OGB6 OGB5 OGB4 OGB3 OGB2 OGB1 OGB0 ORB7 ORB6 ORB5 ORB4 ORB3 ORB2 ORB1 ORB0 tci13 = tcon_in13, orb7 = output red B channel bit 7, rda3 = red A channel bit 3, etc. pwma = pwm_a input ...
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... Table 31: RSDS Mode Specifications clk_o hsync_o o[r,g,b][a,b](2n) 1 bit from 2n 0 bit from 2n ENI INV_A HSI TCI_GATED_CLK VSI INV_B TCI7 TCI7 TCI6 TCI6 TCI5 TCI5 TCI4 TCI4 TCI3 TCI3 TCI2 TCI2 PWM_A TCI1 PWM_B TCI0 o[r,g,b][a,b](2n+1) !bit from 2n !bit from 2n+1 ADE3700 ...
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... ADE3700 Table 31: RSDS Mode Specifications (Continued) RSDS Time clk_o t+2 0 t+3 1 Note: hsync_o is the positive clock signal according to the RSDS definition. 2.19.3 Per Pin Delay Each of the 60 outputs has a per pin programmable delay. The delay is calibrated on the fly to the XCLK period, which is assumed to be 37ns. Each pin can be delayed 6ns in 0.4ns increments. Code 0x0 is the least delay, code 0xF is the maximum delay. The setting is accurate to ± ...
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... R/W [3:0] 0x0 0x0C44 R/W [7:4] 0x0 R/W [3:0] 0x0 ADE3700 Description Separate TCON driven invert enable TCON driven invert pin enable RSDS enable Per Pin Delay Enable Resync on Vsync Falling Edge Resync on Vsync Rising Edge Resync on Hsync Falling Edge Resync on Hsync Rising Edge Delay for OBA1 ...
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... ADE3700 Table 32: Output Mux Registers (Sheet Register Name OMUX_ DLY_BB2 OMUX_ DLY_BB4 OMUX_ DLY_BB6 OMUX_ DLY_GB0 OMUX_ DLY_GB2 OMUX_ DLY_GB4 OMUX_ DLY_GB6 OMUX_ DLY_RB0 OMUX_ DLY_RB2 OMUX_ DLY_R_B4 OMUX_ DLY_R_B6 OMUX_ DLY_TCON_0 OMUX_ DLY_TCON_2 OMUX_ DLY_TCON_4 OMUX_ DLY_TCON_6 OMUX_ DLY_VS_ENAB ...
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... R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 ADE3700 Description Reserved PWM mux mode PWM enable TCON data invert enable, with computed data invert pin. Reserved Returns a value that indicates the ADE gate speed -- a function of temp and voltage higher = faster logic Description PWM status ...
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... ADE3700 Register Name PWM_CTRL1 PWM_PERIOD_L PWM_PERIOD_H PWM_DUTY_L PWM_DUTY_H PWM_OVERLAP_L PWM_OVERLAP_H PWM_STEP_DELAY PWM_CYCLES_PER_FRAME_L PWM_CYCLES_PER_FRAME_H 2.21 DFT Block Register Name DFT_TEST_MODE DFT_MUX_OUT_MODE DFT_FLOP_OUT_MODE DFT_CLK_0UT_MODE DFT_CLK_1_MODE Table 33: PWM Registers (Sheet Addr Mode Bits Default 0x01A1 R/W [7:4] 0x0 R/W [3:0] 0x0 0x01A2 R/W [7:0] 0x0 0x01A3 R/W [7:0] 0x01A4 R/W [7:0] 0x0 0x01A5 R/W [7:0] 0x01A6 ...
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... R [2] R [1] R [0] ADE3700 Description mux selector for clocks to CLKOUT pin Disable Port A Red Output in Test Mode Disable Port A Green Output in Test Mode Disable Port A Blue Output in Test Mode Disable Port B Red Output in Test Mode Disable Port B Green Output in Test Mode ...
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... ADE3700 Register Name DFT_BIST_RESULT_0 DFT_BIST_RESULT_1 DFT_MFSR_DONE DFT_MFSR_SIG_0 DFT_MFSR_SIG_1 DFT_MFSR_SIG_2 DFT_MFSR_SIG_3 2.22 I²C RAM Addresses Name GAM_RED GAM_GREEN GAM_BLUE OSD_MB OSD_CS OSD_DRB SCL_COEFF SCL_LINE1 SCL_LINE2 SCL_LINE3 SCL_LINE4 Table 34: DFT Registers (Sheet Addr Mode Bits Default 0x0F12 [7:6] R [5] R [4] R [3] R [2] R [1] R [0] ...
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... AVDD18 I 1.8V digital supply (I DVDD18 DVDD18 I 3.3V analog supply ( AVDD33 IAVDD33 I 3.3V digital supply (I DVDD33 DVDD33 P Total Power Consumption (Analog Input, XGA@75Hz, 135MHz) TOTANA * Measured at nominal voltage supplies ** Measured at +10% voltage supplies 84/89 Parameter Table 36: ADE3700x Parameter ) ) ) ) Table 37: ADE3700xs Parameter ) ) ) ) ADE3700 Min. Typ. Max. Unit 1.95 V 3.6 V 6.1 ...
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... ADE3700 3.3 Nominal Operating Conditions Symbol AVDD18 Supply Voltage DVDD18 XVDD18 LVDD18 AVDD33 Supply Voltage DVDD33 f Crystal Frequency XTAL T Ambient Operating Temperature OPER 3.4 Preliminary Thermal Data Symbol R Junction-to-Ambient Thermal Resistance, 144-pin package thJA R Junction-to-Ambient Thermal Resistance, 128-pin package thJA 3.5 Preliminary DC Specifications Test Conditions: DVDD33 = AVDD33 = 3 ...
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... Condition Min. Typ. 2.0 VIN = VDD VIN = 0V Condition Min. RSDS mode 100 680 ohm + 50 ohm external 1.1 termination to 1. 30pF no missing codes 0.5 135 MSPS Input = 65 MHz sine at 95 ADE3700 Max. Unit V 0 Max. Unit V 0.8 V -10 µA 10 µA Typ. Max. Unit 200 400 mV 1 ...
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... ADE3700 4 Package Mechanical Data e Pin 1 Identification A2 A1 Dimensions (mm) Min 1.400 b 0.220 D 22.000 D1 20.000 D2 E 16.000 E1 14.000 E2 e 0.500 L 0.600 L1 1.000 0° 0.08/0. 0.08 R. Min. L 0.25 mm. Gauge Plane L1 Typ. Max. 1.600 0.150 1.350 1.450 0.170 0.270 0.450 ...
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... August 2002 0.2 Addition of diagram on Cover. Modification of Description and Product Selector info on 1st page. Modification of Registers. Modification of Registers, 17 October 2002 0.3 Device named changed from ADE3700X to ADE3700. Modification of block diagram and table on cover. 26 Nov 2002 0.4 Modification of registers 4 Dec 2002 0.5 Modification of package data (128-pin LQFP). ...
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... ADE3700 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...