ade3700 STMicroelectronics, ade3700 Datasheet - Page 77

• Manufacturer Part Number: ade3700
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions
• Manufacturer: STMicroelectronics

ADE3700
Note:
2.19.3 Per Pin Delay
OMUX_CTRL_0
OMUX_CTRL_1
hsync_o is the positive clock signal according to the RSDS definition.
Each of the 60 outputs has a per pin programmable delay. The delay is calibrated on the fly to the
XCLK period, which is assumed to be 37ns. Each pin can be delayed by up to 6ns in 0.4ns
increments. Code 0x0 is the least delay, code 0xF is the maximum delay. The setting is accurate to
±0.8ns across PVT. The calibration and resetting is done once per frame after the falling edge of
vertical enable to prevent glitches from delay mux changes in the active data period. The delays are
active in RSDS and normal output modes if enabled in the OUT_MUX_CTRL2 register.
Register Name
t+2
t+3
RSDS Time
Table 31: RSDS Mode Specifications (Continued)
0
1
clk_o
Table 32: Output Mux Registers (Sheet 1 of 4)
0x0C30
0x0C31
Addr
1
0
hsync_o
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[6:4]
[3]
[2]
[1]
[0]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[7]
bit from 2n
bit from 2n+1
Bits
o[r,g,b][a,b](2n)
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0: data invert for A+B comb.
1: data invert A/B separate
0x0 - 0x4: right shift per 8-bit R/G/B
0x5 - 0x7: Reserved
0: normal
1: flip msbs to lsbs
0: normal
1: swap R and B data
0: in 1 ppc, A channel active
0: in 2 ppc, Left on A, Right on B
1: in 1 ppc, B channel active
1: 2ppc, Left on B, Right on A
0: single wide, one pix/clk (ppc)
1: double wide, two pix/clk
Hsync Output Polarity
Data Enable Output Polarity
Clock Output Invert
Data Invert Output Polarity
Data Invert Enable
0: TCON outputs set to zero
1: TCON outputs active
0: all data outputs set to zero
1: output enabled
in 2 ppc,
Vsync Output Polarity
!bit from 2n
!bit from 2n+1
o[r,g,b][a,b](2n+1)
Description
Output Multiplexer
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