ade3700 STMicroelectronics, ade3700 Datasheet - Page 72

• Manufacturer Part Number: ade3700
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions
• Manufacturer: STMicroelectronics

Output Multiplexer
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2.19
rin[7:0]
gin[7:0]
bin[7:0]
tcon_in[13:0]
Output Multiplexer
The Output Multiplexer formats the single wide data stream from the output of the APC block into a
single or double wide data path for the flat panel. The architecture is shown in
Latency is not important, as long as the timing relationship between hsync, vsync, enab and data is
preserved at the output. In Double Wide mode, the first pixel must be properly aligned even if the
number of pixels in blanking or active are odd. The divide-by-2 circuit can be set to resync per line
(based on data_enab and hsync_in edge) and per frame (based on vsync_in edge). The most
reliable timing is when hsync and vsync are in the “low” counts of the timing core counters (i.e.
hsync_set and hsync_rst are both below the active data region start/end counts). In the event that
hsync and vsync are in the “high” (after active region) counts, the device should be set to sync to
data_enab_re.
The Per Pin Delay and RSDS logic occur after the last latch and are implemented on all channels to
maintain delay balance between signals that go into RSDS mode (data and clk/hsync) and those
that do not (de/vsync and tcon).
pwm_a_in
pwm_b_in
hsync_in
vsync_in
enab_in
8
8
8
Right
Right
Right
Shift
Shift
Shift
2
14
8
8
8
Figure 10: Output Mux Block Diagram
Byte
Byte
Byte
Flip
Flip
Flip
8
8
8
tci[13:0]
Red &
Swap
Blue
tcon_out[7:0]
24
Double Wide
8
Converter
Single to
RSDS Logic and Per Pin Delay
FLOPS
routa[7:0]
gouta[7:0]
bouta[7:0]
routb[7:0]
goutb[7:0]
boutb[7:0]
hclk
48
Output Mux/Reg
rda[7:0]
gda[7:0]
bda[7:0]
rdb[7:0]
gdb[7:0]
bdb[7:0]
enab_out
hsync_out
vsync_out
48
3
Figure
48
Inversion
10.
Data
inv_a
inv_b
clk_out
ADE3700
2