bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 176

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bt8375kpf

Manufacturer Part Number
bt8375kpf
Description
Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
Manufacturer
Conexant Systems, Inc.
Datasheet

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3.9 Performance Monitoring Registers
3.9 Performance Monitoring Registers
Unused bits indicated by a dash (
effect.
counter, the counter rolls over after reaching its maximum count value. If the overflow interrupt is disabled, the
counter holds maximum value upon saturation. Refer to LATCH [addr 046] for a description of 1-second
latched counter operation. The processor must read the Least Significant Byte (LSB) before reading the Most
Significant Byte (MSB) of each multi-byte counter.
FERR[7:0]
If LATCH_CNT [addr 046] is inactive, reading FERR [addr 051] clears the entire FERR[11:0] count value.
FERR[11:8]
CERR[7:0]
3-58
050— Framing Bit Error Counter LSB (FERR)
051— Framing Bit Error Counter MSB (FERR)
052— CRC Error Counter LSB (CERR)
If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective performance monitoring
CERR[7]
FERR[7]
15
7
0
7
Ft/Fs/T1DM/FPS/FAS Error Count
Ft/Fs/T1DM/FPS/FAS Error Count
CRC6/CRC4 Error Count
CERR[6]
FERR[6]
14
6
0
6
CERR[5]
FERR[5]
13
5
0
5
) are reserved and should be written to 0. Writing to reserved bits has no
CERR[4]
FERR[4]
12
4
0
4
Conexant
FERR[11]
CERR[3]
FERR[3]
11
3
3
Fully Integrated T1/E1 Framer and Line Interface
FERR[10]
FERR[2]
CERR[2]
10
2
2
FERR[9]
CERR[1]
FERR[1]
Bt8370/8375/8376
1
9
1
N8370DSE
FERR[8]
CERR[0]
FERR[0]
0
8
0

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