sp5502 Mitel, sp5502 Datasheet - Page 3

• Manufacturer Part Number: sp5502
• Description: 1.3ghz I2c Bus 4-address Synthesiser
• Manufacturer: Mitel

ing the programmed division ratio by 8 times the comparison
frequency F
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the program-
mable divider is frequency and phase locked to the comparison
frequency.
source capacitively coupled into pin 2 or provided by an on-
chip 4MHz crystal controlled oscillator.
4MHz reference is used.
current in the charge pump circuit, a logic 1 for
a logic 0 for
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
The programmed frequency can be calculated by multiply-
When frequency data is entered, the phase comparator,
The reference frequency may be generated by an external
Note that the comparison frequency is 7·8125kHz when a
Bit 2 of Byte 4 of the programming data (CP) controls the
COMP
50µA, allowing compensation for the variable
NOTES
† Programmed by connecting a 15k
*
.
Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
Address
Status byte
Don’t care condition on SP5502F.
A
MA1, MA0
CP
T1
T0
OS
P7, P4
POR
FL
X
N
Table 1 Write data format (MSB transmitted first)
*
, P2, P1, P0
MSB
POR
MA1
P7
2
170µA and
1
0
1
1
0
0
1
1
7
Table 3 Address selection
Table 2 Read data format
Fig. 3 Data formats
MA0
*
2
CP
FL
: Acknowledge bit
: Variable address bits (see Table 3)
: Charge Pump current select
: Test mode selection
: Charge pump disable
: Varactor drive Output disable Switch
: Power On Reset indicator
: Phase lock detect flag
: Don’t care
: Not valid
2
resistor between Address Select Port P3 and V
X
1
1
0
1
0
1
14
6
:
Voltage input to P3
2
0·4V
T1
2
N
X
0
0
13
Control output port states
5
0·9V
0V to 0·1V
Open circuit
CC
P4
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P2 and P7, a logic
1 connects F
SP5502S (P1, P2 and P7 only on SP5502F), a logic 0 for a
high impedance output, logic 1 for low impedance (on).
READ MODE
the device on the SDA line takes the form shown in Table 2. Bit
1 (POR) is the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when the
device is initially turned on). The POR is set to 0 when the read
sequence is terminated by a stop command. The outputs are all
set to high impedance when the device is initially powered up. Bit
2 (FL) indicates whether the device is phase locked, a logic 1 is
present if the device is locked and a logic 0 if the device is
unlocked.
2
T0
2
N
0
0
CC
12
4
to 0·6V
*
Byte 5 programs the output ports P0-P2, P4 and P7 on the
When the device is in the read mode the status data read from
to V
2
2
X
N
0
1
0
11
CC
3
CC
CC
MA1
MA1
†
2
P2
2
N
1
10
COMP
2
MA0
MA0
P1
2
2
N
1
to P2 and F
9
1
LSB
P0
OS
2
2
N
1
0
8
0
*
A
A
A
A
A
A
A
DIV
to P7.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
CC
.
3