mh89760b Mitel, mh89760b Datasheet
mh89760b
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mh89760b Summary of contents
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... ST-BUS FAMILY MH89760B MH89760BN MH89760BS Description The MH89760B is a complete T1 interface solution, meeting the Extended Super Frame (ESF), D3/D4 and SLC-96 formats. The MH89760B interfaces to the DS11.544 Mbit/sec digital trunk. The MH89760B is a pin-compatible enhancement of the MH89760, permitting the removal of the tuneable inductor and inclusion of the external NAND gate used for generating RxD ...
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... MH89760B Pin Description Pin # Name Connection. 3 E1.5o 1.544 MHz Extracted Clock (Output): This clock is extracted by the device from the received DS1 signal used internally to clock in data received at RxT and RxR System Power Supply. +5V RxA Received A (Output): The bipolar DS1 signal received by the device at RxR and RxT is converted to a unipolar format and output at this pin ...
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... RxT and RxR inputs. When LOS is high, RxA and RxB are forced high. LOS is reset when 48 ones are received in a two T1-frame period Connection Connection. MH89760B Description bit pattern when kbit/s serial input stream that is muxed into the : pattern when in SLC96 mode clocked in on the S ...
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... MH89760B 4-58 Preliminary Information ...
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... ST-BUS stream, and one of these 64 kbit/s channels is known as an ST-BUS channel. The system side of the MH89760B is made up of ST- BUS inputs and outputs, i.e., control inputs and outputs (CSTi/o) and data inputs and outputs (DSTi/o). These signals are functionally represented in Figure 32 ...
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... MH89760B Bit Name 7 Debounce When set the received and D signalling bits are reported directly in the per channel status words output at CSTo. When clear, the signalling bits are debounced for before they are placed on CSTo. 6 TSPZCS Transparent Zero Code Suppression. When this bit is set, no zero code suppression is implemented ...
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... Zero Code Suppression or T The combination of bits 5 and 6 in Master Control Word 1 allow one of three zero code suppression schemes to be selected. The three choices are: none, binary 8 zero suppression (B8ZS), or jammed bit (bit 7 forced high). No zero code suppression MH89760B † Signalling ...
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... MH89760B Frame † Resynchronization =Concentrator ...
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... C, D bits, the values of C and D are ignored. Table 7. Per Channel Control Word 2 Input at CSTi1 MH89760B The MH89760B also has a per channel loopback mode. See Table 6 and the following section for more information. Per Channel Control Features In addition to the two master control words in CSTi0 there are also 24 Per Channel Control Words ...
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... Description of the bits in Master Status Words 1 and 2, and Table 10 gives a description of the Phase Status Word. In addition, the MH89760B has a Loss of Signal (LOS) pin that is set High when 128 consecutive ZEROs are received. While LOS is set High, RxA and RxB are forced High. The LOS signal goes Low when a ONEs density on 12 ...
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... In such a system, the local 2.048 MHz clock is derived from a precision VCO. Frequency corrections are made on the basis of the average trend observed in MH89760B . 4-65 ...
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... F0i which in turn is derived from the same source as the C2 clock set up to generate the ST-BUS clocks that are phase locked to the received data rate. If E8Ko from the MH89760B is connected to the C8Kb input on terminal frame the MT8941, DPLL #2 in the device will generate the ST-BUS clocks that are phase locked to the T1 line ...
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... The capacitor and inductor on the center tap of the transmit transformer shown in Figure 6 suppress transients in the 12 volt supply. The series RLC across the output of the transformer shape the pulse to meet the AT & CCITT pulse templates. A MH89760B MH89761 EIT EIR TxT TxR ...
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... RxA and RxB. The input jitter tolerance of the MH89760B is shown in Figure 7. Elastic Buffer The MH89760B has a two frame elastic buffer which absorbs jitter in the received DS1 signal. The buffer is also used in the rate conversion between the 1.544 Mbit/s DS1 rate and the 2.048 Mbit/s ST-BUS data rate ...
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... One of the main features of the framer is that it performs its function "off line". That is, the framer repositions the receive circuit only when it has MH89760B pattern, i.e declare valid terminal ...
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... MH89760B Hunt Mode Candidate Candidate Verify Candidate In sync New Frame Position * Note: Only when in ESF mode and CRC option is enabled. detected a valid frame position. When the framer exits maintenance mode the receive counters remain where they are until the framer has found a new frame position ...
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... MT8941, provides all the clocks necessary to make a functional interface. The 1.544 MHz clock extracted by the MH89760B is used to clock in data at RxT and RxR also internally divided by 193 to obtain an 8 kHz clock which is output at E8Ko. The MT8941 uses this 8 kHz signal to provide a phase locked 2 ...
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... RCHR TR2 RECEIVE 1: R1=150 1%, 1/4w R2 4. 250V 100V 130mA 165mA TR1 & TR2 see Figures 6 & 11 Line Side MH89760B • • • Output Transformer Units 100 (4-8) 0.46 mH (1-5):(4-8) 1.89:1 (2-6):(4-8) 1.89:1 1500 V(rms) TxT TxR ...
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... IRQ IACK MMS +5V Figure 12 - Using the MH89760B in a Parallel Bus Environment the signalling and link control bus to the MH89760B status and control channels. All signalling and link functions may be controlled easily through the STPA transmit RAM’s Tx0, Tx1, while status information is read at receive RAM Rx0 ...
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... The data received from the MT8910 is then transferred to the D channel processor by the switch matrix. The D channel processor converts the 2B+D format used on the 160 kBit digital line into the 23B+D format used on the T1 Link. Preliminary Information T1 Interface MH89760B DSTi OUTA Equal- DSTo izer OUTB ...
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... There are four main blocks in Figure 15, the T1 interfaces, the switch matrix, the control matrix, and the clock generator. The digital trunk interface is made up of the MH89760B plus the additional components required to interface to the transmission line. The MH89760B handles all of the required transmit and receive data formatting, and converts the 1 ...
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... Phase-locked Loop #2 of the MT8941, will generate ST-BUS clock signals for the MH89760Bs and the MT8980s that are synchronized with the chosen T1 line. The E8Ko of all of the other MH89760Bs can be tristated from the Master Control Word, which allows the system controller to select any one of 128 T1 lines to act as the synchronization source ...
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... Figure 16 - Digital Multiplex Interface (DMI) protocol converter (micro and MT8952s), the switch matrix (MT8980), and the T1 interface (MH89760B). The Asynchronous Adapters (ACIA) provide a standard RS232 interface that is compatible with many off-the-shelf modems and data sets. A single microprocessor is capable of handling the protocol conversion between the RS232 ports and the MT8952 HDLC protocol controller ...
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... The switch matrix switches the first 24 channels received from the protocol section into the 24 valid timeslots used by the MH89760B. Once the data enters the T1 interface the MH89760B formats and transmits the data on the T1 line. ...
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... DSP Element STi0 STo1 STo0 STi1 STo3 STi2 STo4 STo2 STi4 STo3 C4i F0i P MT8941 DPLL #1 C1.5o DPLL #2 F0o C2o E8Ki C4o Clock Generator MH89760B Therefore CEPT T1 Interface MH89760B RxT DSTi RxR DSTo CSTo CSTi0 OUTA CSTi1 F0i OUTB C2i C1.5i E8Ko 4-79 ...
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... Figure 11. Alternatively, they are available directly from the following manufacturer: Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 Telephone: (613) 226-1626 Please refer to Figure 6 for the transformer part numbers. Preliminary Information initial design activities, Mitel has available the MH89760B ...
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... 0. 400 4 1.5 T- † - Capacitance ‡ Sym Min Typ Max MH89760B Min Max Units -0 -0 200 mW - unless otherwise stated. SS Units Test Conditions ° Digital Inputs V Line Inputs ...
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... MH89760B AC Electrical Characteristics Characteristics 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Hold Time 5 Frame Pulse Width 6 RxSF Output Delay 7 TxSF Hold Time 8 TxSF Setup Time NB: Frame Pulse is repeated every 125 s in synchronization with the clock. ...
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... ST-BUS Streams (Figure 22) ‡ Sym Min Typ Max t 125 SOD t 15 SIS t 50 SIH Bit Cell Boundaries t t SIH SIS Figure 22 - ST-BUS Stream Timing MH89760B Units Test Conditions BIT CELL t t R1EC W1EC Units Test Conditions ns 150 pF load SOD 4-83 ...
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... MH89760B AC Electrical Characteristics Parameters 1 External Control Delay 2 External Status Setup Time 3 External Status Hold Time 4 8 kHz Output Delay 5 8 kHz Output Low Width 6 8 kHz Output High Width 7 8 kHz Rise Time 8 8 kHz Fall Time † Timing is over recommended temperature & power supply voltage ranges. ...
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... Bit Cell t PC1.5 t WC1 TSD TSD Figure 26 - Transmit Timing for DS1 Link Bit Cell t PEC t WEC t t RDS RDH t RDW t RDF Figure 27 - Receive Timing for DS1 Link MH89760B Units Test Conditions ns 150 pF Load WEC t RDR 4-85 ...
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... MH89760B AC Electrical Characteristics Parameters 1 Transmit FDL Setup Time 2 Transmit FDL Hold Time 3 Receive FDL Output Delay 4 Receive FDL Clock Delay 5 Transmit FDL Clock Delay † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are and are for design aid only; not guaranteed and not subject to production testing ...
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... Figure 32 - Functional ST-BUS Timing 125 Figure 33 - Functional DS1 Receive Timing MH89760B CHANNEL CHANNEL 31 0 Least BIT 2 BIT 1 BIT 0 Significant Bit (Last) S Bit CHANNEL CHANNEL 24 1 ...
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... MH89760, has a row pitch of 1.3” and is fitted with a plastic lid. See Figure 37 for the dimensional drawing for this part. • The MH89760BN which is a narrow version of the MH89760B and has a row pitch of 0.8”. See Figure 38 for the dimensional drawing for this part. 0.06 (1.52) ...
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... Pin 1 not fitted. 2) Row pitch is to the centre of the pins. 3) All dimensions are typical and in inches (mm). 4) Not to scale. Figure 37 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 1.3" Row Pitch 0.760 (19.3) 0.060 (1.52) 0.10 + 0.01 (2.54 + 0.25) MH89760B .31 (7.87) 1.3 (33.0) Note 2 AAAA AAAA AAAA AAAA AAAA AAAA ...
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... MH89760B MH89760BN Note 1 Notes: 1) Pin 1 not fitted. 2) Row pitch is to the centre of the pins. 3) All dimensions are typical and in inches (mm). 4) Not to scale. Figure 38 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 0.8" Row Pitch 4-90 2.0 (50.8) 0.10 + 0.01 (2.54 + 0.25) Preliminary Information AAAA AAAA AAAA AAAA ...
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... MFSYNC 1 Detected 1 Not Detected 0 Not 0 Detected Detected Master Status Word 1 (Channel 15, CSTo) BIPOLAR VIOLATION COUNT Master Status Word 2 (Channel 31, CSTo) Phase Status Word (Channel 3, CSTo) A Rec’d. Sig. Bit MH89760B 2 1 ESFYLW Robbed Bit YLALR 1 Enabled 1 Disabled 1 Enabled 0 Disabled 0 Enabled 0 Disabled ...
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... MH89760B Notes: 4-92 Preliminary Information ...