SCC68692C1F40 PHILIPS [NXP Semiconductors], SCC68692C1F40 Datasheet - Page 10

• Manufacturer Part Number: SCC68692C1F40
• Description: Dual asynchronous receiver/transmitter DUART
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
zeros will be loaded into the RHR and the received break bit in the
SR is set to 1. The RxD input must return to high for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will
usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
Receiver FIFO
The RHR consists of a First-In-First-Out (FIFO) stack with a
capacity of three characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
In the ‘block’ mode, the status provided in the SR for these three bits
is the logical-OR of the status for all characters coming to the top of
the FIFO since the last ‘reset error’ command was issued. In either
mode reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore the status register
should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exits, the
contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4] will be
set-upon receipt of the start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted
automatically. This feature can be used to prevent an overrun, in
the receiver, by connecting the RTSN output to the CTSN input of
the transmitting device.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register data, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers. This has the appearance of “clearing or
flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!
The data in the FIFO remains valid until overwritten by another
received character. Because of this, erroneous reading or extra
reads of the receiver FIFO will miss-align the FIFO pointers and
result in the reading of previously read data. A receiver reset will
re-align the pointers.
1998 Sep 04
Dual asynchronous receiver/transmitter (DUART)
10
bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.
Timeout Mode
The timeout mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RHR, the counter is restarted. If a new character is
not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the Rx FIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTU and CTL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new
data during the programmed time interval, the counter ready bit will
get set, and an interrupt can be generated.
This mode is enabled by writing the appropriate command to the
command register. Writing an ‘Ax’ to CRA or CRB will invoke the
timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will
disable the timeout mode. The timeout mode should only be used
by one channel at once, since it uses the C/T. CTU and CTL must
be loaded with a value greater than the normal receive character
period. The timeout mode disables the regular START/STOP
Counter commands and puts the C/T into counter mode under the
control of the received data stream. Each time a received character
is transferred from the shift register to the RHR, the C/T is stopped
after 1 C/T clock, reloaded with the value in CTU and CTL and then
restarted on the next C/T clock. If the C/T is allowed to end the
count before a new character has been received, the counter ready
Since receiving a character after the C/T has timed out will clear the
counter ready bit, ISR[3], and the interrupt. Invoking the ‘Set
Timeout Mode On’ command, CRx = ‘Ax’, will also clear the counter
ready bit and stop the counter until the next character is received.
This mode is reset by the “Disable Time-out Mode” command (CR
x’C0) must be used.
Time Out Mode Caution
When operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time-out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data strea.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
Multidrop Mode
The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this
mode of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
the received data stream and ‘wake up’ the CPU (by setting RxRDY)
SCC68692
Product specification