SCC68692C1F40 PHILIPS [NXP Semiconductors], SCC68692C1F40 Datasheet - Page 20

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SCC68692C1F40

Manufacturer Part Number
SCC68692C1F40
Description
Dual asynchronous receiver/transmitter DUART
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
Philips Semiconductors
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTUR and CTLR.
1998 Sep 04
Dual asynchronous receiver/transmitter (DUART)
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
DTACKN
X1/CLK
A1–A4
D0–D7
RWN
CSN
RESET
t
DA
t
AS
Figure 4. Bus Timing (Read Cycle)
t
VALID
RWS
t
NOT
DD
t
CSC
Figure 3. Reset Timing
t
AH
t
DAL
t
t
RES
DCR
20
DATA VALID
IVR – Interrupt Vector Register
This register contains the interrupt vector. The register is initialized
to H‘0F’ by RESET. The contents of the register are placed on the
data bus when the DUART responds to a valid interrupt
acknowledge cycle.
t
CSD
t
DAT
SD00028
t
CSW
t
t
RWH
t
DAH
DF
SD00147
SCC68692
Product specification

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