SI5013-X-GM ETC1 [List of Unclassifed Manufacturers], SI5013-X-GM Datasheet - Page 12

• Manufacturer Part Number: SI5013-X-GM
• Description: OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Si5013
4. Functional Description
The Si5013 integrates a high-speed limiting amplifier
with a multi-rate CDR unit. No external reference clock
is required for clock and data recovery. The limiting
amplifier magnifies very low-level input data signals so
that accurate clock and data recovery can be
performed. The CDR uses Silicon Laboratories®
DSPLL technology to recover a clock synchronous to
the input data stream. The recovered clock retimes the
incoming data, and both are output synchronously via
current-mode logic (CML) drivers. Silicon Laboratories’
DSPLL technology ensures superior jitter performance
while eliminating the need for external loop filter
components found in traditional phase-locked loop
(PLL) implementations.
The limiting amplifier includes a control input for
adjusting the data slicing level and provides a loss-of-
signal level alarm output. The CDR includes a bit error
rate performance monitor which signals a high bit error
rate condition (associated with excessive incoming
jitter) relative to an externally adjustable bit error rate
threshold.
The optional reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to a reference
is desired.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the CDR unit. The
minimum input swing requirement is specified in Table 2
on page 7. Larger input amplitudes (up to the maximum
input swing specified in Table 2) are accommodated
without degradation of performance. The limiting
amplifier ensures optimal data slicing by using a digital
dc offset cancellation technique to remove any dc bias
introduced by the amplification stage.
4.2. DSPLL
The Si5013 PLL structure (shown in the "1.Detailed
Block Diagram" on page 4) utilizes Silicon Laboratories'
DSPLL
performance while eliminating the need for external loop
filter
implementations. This is achieved using a digital signal
processing (DSP) algorithm to replace the loop filter
commonly found in analog PLL designs. This algorithm
processes the phase detector error term and generates
a digital control value to adjust the frequency of the
voltage-controlled oscillator (VCO). This technology
enables CDR with far less jitter than is generated using
12
components
technology
™
found
to
maintain
in
traditional
superior
jitter
PLL
Rev. 1.4
traditional methods, and it eliminates performance
degradation caused by external component aging. In
addition, because external loop filter components are
not required, sensitive noise entry points are eliminated,
thus making the DSPLL less susceptible to board-level
noise
compliance easier to attain in the application.
4.3. Multi-Rate Operation
The Si5013 supports clock and data recovery for OC-
12/3 and STM-4/1 data streams.
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The divide factor is configured by the
RATESEL pin. The RATESEL configuration and
associated data rates are given in Table 7.
4.4. Operation Without an External Refer-
The Si5013 can perform clock and data recovery
without
REFCLK+ input to VDD and the REFCLK– input to
GND configures the device to operate without an
external reference clock. Clock recovery is achieved by
monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
Note: Without an external reference the acquisition of data is
4.5. Operation With an External Reference
The Si5013 can also perform clock and data recovery
with an external reference. The device’s optional
external reference clock centers the DSPLL, minimizes
the acquisition time, and maintains a stable output clock
(CLKOUT) when lock-to-reference (LTR) is asserted.
When the reference clock is present, the Si5013 uses
the reference clock to center the VCO output frequency
so that clock and data is recovered from the input data
stream. The device self configures for operation with
one of three reference clock frequencies. This
ence
dependent solely on the data itself and typically
requires more time to acquire lock than when a refer-
ence is applied.
sources
Table 7. Multi-Rate Configuration
an external
RATESEL SONET/SDH
and
1
0
reference clock.
making
622.08 Mbps
155.52 Mbps
SONET/SDH
Tying
jitter
the