SI5013-X-GM ETC1 [List of Unclassifed Manufacturers], SI5013-X-GM Datasheet - Page 23

• Manufacturer Part Number: SI5013-X-GM
• Description: OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

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Revision 0.2 to Revision 1.0
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Revision 1.0 to Revision 1.1
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OCUMENT
Added Figure 4, “PLL Acquisition Time,” on page 6.
Table 2 on page 7
z
z
z
z
Table 3 on page 8
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z
z
Table 4 on page 9
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z
z
z
z
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z
Removed “Hysteresis Dependency” Figure.
Added Figure 7, “LOS Signal Hysteresis,” on page
13.
Corrected error: Table 8 on page 18—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
Corrected “Revision 0.2 to Revision 1.0” Change
List.
Table 4 on page 9
z
(REFCLK)
applied)
(reference-less operation)
goes out of Lock
goes into Lock
Updated values: Supply Current
Updated values: Power Dissipation
Updated values: Common Mode Input Voltage
Updated values: Output Common Mode Voltage
Updated values: Output Clock Rise Time
Updated values: Output Clock Fall Time
Updated values: Clock to Data Delay t
Updated values: Jitter Tolerance (OC-12)
Updated values: RMS Jitter Generation
Updated values: Peak-to-Peak Jitter Generation
Updated values: Acquisition Time (reference clock
Updated values: Acquisition Time
Updated values: Freq Difference at which Receive PLL
Updated values: Freq Difference at which Receive PLL
Updated values: Jitter Tolerance (OC-3)
C
HANGE
L
IST
Cf-D
Rev. 1.4
Revision 1.1 to Revision 1.2
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Revision 1.2 to Revision 1.3
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Revision 1.3 to Revision 1.4
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Added Figure 5, “LOS Response,” on page 6.
Updated Table 2 on page 7.
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updated values.
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updated values.
Updated Table 3 on page 8.
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z
values.
Updated Table 8 on page 18.
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Updated Figure 16, “28-Lead Micro Leaded Package
(MLP),” on page 22.
Updated Table 9, “Package Diagram Dimensions,”
on page 22.
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z
Updated Figure 16, “28-Lead Micro Leaded Package
(MLP),” on page 22.
Updated Table 9, “Package Diagram Dimensions,”
on page 22.
Updated "Features" on page 1.
Table 2 on page 7.
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Table 3 on page 8.
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z
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Table 4 on page 9.
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"3.Typical Application Schematic" on page 11.
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"4.11.PLL Performance" on page 14.
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Table 8 on page 18.
z
Updated "6.Ordering Guide" on page 21.
z
Added “Output Common Mode Voltage (CLKOUT)” with
Added “Output Common Mode Voltage (DOUT)” with
Added “Output Clock Duty Cycle—OC-12/3.”
Added “Loss-of-Signal Response Time” with updated
Changed “clock input” to “DIN inputs” for Loss Of Signal
Changed dimension A.
Changed dimension E2.
Updated supply current values.
Updated power dissipation values.
Updated differential output voltage swing
(DOUT and CLKOUT).
Added output clock rate values.
Updated duty cycle values.
Updated slice accuracy values.
Updated jitter tolerance values (OC-12 mode).
Updated acquisition time values.
Updated reference clocks range.
Updated reference clocks tolerance.
Added 1% to Rext.
Removed OC-24 note.
Added no-hysteresis text to BER_LVL.
Added “X” to part number.
Si5013
23