k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 18

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
GENERAL INFORMATION
dance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and
the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V4 of 136 ball package.
For the normal device operation other than boundary scan, there required device re-initialization by device power-off and then power-on.
DISABLING THE SCAN FEATURE
LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF,
WDQS0 and CS# will be operating at normal GDDR3 function when SEN is de-asserted.
7.7 BOUNDARY SCAN FUNCTION
The 256Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn’t operate in accor-
It is possible to operate the 256Mb GDDR3 without using the boundary scan feature. SEN(at V-4 of 136 ball package) should be tied
Pins under test
RFU at V-4 (SEN, Scan Enable)
MF (SOE#, Output Enable)
WDQS0 (SOUT,Scan Out)
CS# (SCK, Scan Clock)
RES (SSH,Scan Shift)
RDQS0
DQ4
DQS
DM0
Figure 1. Internal Block Diagram (Reference Only)
Tie to Iogic 0
Puts device into scan mode and re-maps pins to scan functionality
D
D
D
D
CK
CK
CK
CK
DQ
DQ
DQ
DQ
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The following lists the rest of the signals on the scan chain:
DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], RFU,
CAS#, WE#, CKE, BA[1:0], A[11:0], CK, CK# and ZQ
Two RFU’s(J-2 and J-3 on 136-ball package) and one
RFM(H-10 on 136-ball package) will be on the scan chain
and will be read as a logic "0"
The following lists signals not on the scan chain:
NC, VDD, VSS, VDDQ, VSSQ, VREF
In case ZQ pin is connected to the external resistor, it will
be read as logic "0". However, if the ZQ pin is open, it will
be read as floating. Accordingly, ZQ pin should be driven
by any signal.
Dedicated Scan Flops
(1per signal under test)
256M GDDR3 SDRAM
Rev. 1.3 May 2007