k9k1208u0m-ycb0 Samsung Semiconductor, Inc., k9k1208u0m-ycb0 Datasheet - Page 22

• Manufacturer Part Number: k9k1208u0m-ycb0
• Description: 64m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 2 for main array and 3 for spare array. The addressing may be done in
any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
K9K1208U0M-YCB0, K9K1208U0M-YIB0
Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low)
R/B
I/O
Figure 7. Program & Read Status Operation
R/B
I/O
0
0
~
~
7
7
50h
80h
(A
Don t Care)
Start Add.(4Cycle)
A
4
0
~ A
~ A
A
Address & Data Input
0
7
528 Byte Data
3
~ A
:
& A
7
9
& A
~ A
9
25
~ A
25
t
R
10h
Data Field
Data Output
1st
22
t
PROG
Spare Field
t
R
1st
Nth
Data Output
Block
(16Byte)
2nd
70h
FLASH MEMORY
t
R
Fail
I/O
0
Data Output
(16Byte)
Nth
Pass