msm82c54-2rs Oki Semiconductor, msm82c54-2rs Datasheet - Page 19

• Manufacturer Part Number: msm82c54-2rs
• Description: Cmos Programmable Interval Timer
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Note:
Note:
D
1
1
1
1
1
1
7
D
Null count indicates the count value finally written in the counter register (CR) has been
loaded in the counter element (CE). The time when the count value was loaded in the CE
depends on the mode of each counter, and it cannot be known by reading the counter value
because the count value does not tell the new count value if the counter is latched. The null
count operation is shown below.
If status latching is carried out multiple times before status reading, other than the first
status latch is ignored.
Simultaneous latching of the count and status of the selected counter is also possible. For
this purpose, set bits D
same as writing two separate read back commands at the same time. If counter/status
latching is carried out multiple times before each reading, other than the first one is ignored
here again. The example is shown below.
If both the count and status are latched, the status latched in the first counter read operation
is read. The order of count latching and status latching is irrelevant.
The count(s) of the next one or two reading operations is or are read.
1
1
1
1
1
1
6
Note: The null count operation for each counter is independent. When the 2-byte count
Operation
A. Control word register writing
B. Count register (CR) writing
C. New count loading to CE (CRÆCE)
D
Command
0
1
1
0
0
1
5
The latch command at this time point is ignored, and the first latch command is valid.
There is the possibility of glitch noise in the output low level when reading out the data.
Peak voltage in typical condition (5 V, 25 C) is approximately 1V and in the worst
condition (5.5 V, –40 C) is approximately 1.4V.
D
0
0
0
1
0
0
4
is programmed, the null count is set to 1 when the count value of the second byte
is written.
D
0
0
1
1
0
0
3
D
0
1
1
0
1
0
2
D
1
0
0
0
0
1
1
D
0
0
0
0
0
0
0
Read back status and count
(counter 0)
Read back status (counter 1)
Read back status (counter 1 and 2)
Read back status (counter 2)
Read back status and count
(counter 1)
Read back status (counter 0)
4
and D
3
, COUNT and STATUS bits, to 00. This is functionally the
Contents
Null count = 1
Null count = 1
Null count = 0
Result
Count Status Count Status Count Status
Counter 0
L
L
L
L
L
L
(NOTE)
L
L
L
L
L
L
MSM82C54-2RS/GS/JS
Counter 1
—
—
—
—
L
L
(NOTE)
(NOTE)
—
L
L
L
L
L
Counter 2
—
—
—
L
L
L
19/23
—
—
L
L
L
L