msm82c55a-2rs Oki Semiconductor, msm82c55a-2rs Datasheet - Page 13

• Manufacturer Part Number: msm82c55a-2rs
• Description: Cmos Programmable Peripheral Interface
• Manufacturer: Oki Semiconductor

¡ Semiconductor
2. Mode 1 (Strobe input/output operation)
Type
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
In mode 1, the strobe, interrupt and other control signals are used when input/output
operations are made from a specified port. This mode is available for both groups A and
B. In group A at this time, port A is used as the data line and port C as the control signal.
Following is a description of the input operation in mode 1.
STB (Strobe input)
When this signal is low level, the data output from terminal to port is fetched into the
internal latch of the port. This can be made independent from the CPU, and the data is not
output to the data bus until the RD signal arrives from the CPU.
IBF (Input buffer full flag output)
This is the response signal for the STB. This signal when turned to high level indicates that
data is fetched into the input latch. This signal turns to high level at the falling edge of STB
and to low level at the rising edge of RD.
INTR (Interrupt request output)
This is the interrupt request signal for the CPU of the data fetched into the input latch. It
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to
high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge
of the RD when the INTE is set.
INTE
bit for PC
Following is a description of the output operation of mode 1.
Notes: When used in mode 0 for both groups A and B
D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
A
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
of group A is set when the bit for PC
6
2
D
Control Word
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
is set.
5
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
3
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Port A
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Group A
High Order 4 Bits
4
is set, while INTE
of Port C
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
MSM82C55A-2RS/GS/VJS
Port B
B
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
of group B is set when the
Group B
Low Order 4 Bits
of Port C
Output
Output
Output
Output
Output
Output
Output
Ouput
Input
Input
Input
Input
Input
Input
Input
Input
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