UPD43256BGW-B12-9JL NEC [NEC], UPD43256BGW-B12-9JL Datasheet - Page 14

• Manufacturer Part Number: UPD43256BGW-B12-9JL
• Description: 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT
• Manufacturer: NEC [NEC]

•
Write Cycle Timing Chart 1 (/WE Controlled)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
14
I/O (Input / Output)
Address (Input)
2. When I/O pins are in the output state, therefore the input signals must not be applied to
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O
/WE (Input)
/CS (Input)
the output.
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
pins will remain high impedance state.
Indefinite data out
t
AS
Data Sheet M10770EJCV0DS00
t
WHZ
t
AW
t
CW
t
WC
impe-
dance
High
t
WP
t
DW
Data in
t
t
WR
DH
t
OW
High
impe-
dance
Indefinite data out
PD43256B