oxfw911 ETC-unknow, oxfw911 Datasheet - Page 11

• Manufacturer Part Number: oxfw911
• Description: Ieee1394 To Ata/atapi Native Bridge
• Manufacturer: ETC-unknow

Data Sheet Rev 1.1
OXFORD SEMICONDUCTOR LTD.
Symbol
t2cyctyp
tiordyz
tziordy
t2cyc
tdvs
tdvh
tzah
tzad
tenv
tcyc
tack
tds
tdh
tmli
taz
trfs
trp
tss
tfs
tui
tli
Parameter
Typical sustained average two
cycle time
Cycle time allowing for clock
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(from data bus being valid until
STROBE edge )
Data valid hold time at sender
(from STROBE edge until data
may become invalid
First STROBE time (for device to
first
STOP during a data-in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from being
asserted or negated)
Minimum delay time required for
output drivers to assert or negate
(from released state)
Envelope time ( from DMACK# to
STOP and HDMARDY# during
data-out burst initiation
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate
pause after negating DMARDY# )
Pull-up
IORDY to be released
Minimum time a device shall wait
before driving IORDY
Setup
DMACK# (before assertion or
negation )
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender terminates
a burst )
negate
after
and
time
the
hold
DSTROBE
before
negation
times
Table 7a: OXFW911 Ultra DMA timings (cont)
allowing
from
for
of
Mode 3
min
100
100
39
86
20
20
20
20
20
50
7
5
6
0
0
0
0
0
Mode 3
max
130
100
10
55
60
20
Mode 4
min
100
60
25
57
20
20
20
20
50
5
5
6
6
0
0
0
0
0
Mode4
max
120
100
10
55
60
20
Mode5
min
4.0
4.6
4.8
4.8
40
20
40
20
20
50
0
0
0
Mode5
max
90
75
20
10
20
50
50
85
20
0
0
OXFW911
Page 11
Unit
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ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s