oxfw911 ETC-unknow, oxfw911 Datasheet - Page 5

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oxfw911

Manufacturer Part Number
oxfw911
Description
Ieee1394 To Ata/atapi Native Bridge
Manufacturer
ETC-unknow
Datasheet

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Manufacturer:
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3 P
Power and ground
Data Sheet Rev 1.1
1394 PHY-LINK interface
ARM external interface
IDE interface
EEPROM interface
Miscellaneous Pins
104, 105, 108, 109, 110, 111, 114,
15, 8, 40, 48, 59, 76, 94, 107, 113
2, 3, 4, 5, 6, 9, 10, 11, 12, 13, 16,
35, 36, 37, 38, 41, 42, 43, 44, 45,
86, 82, 80, 78, 74, 72, 70, 66, 65,
OXFORD SEMICONDUCTOR LTD.
46, 49, 50, 51, 52, 53, 54, 60
30, 21, 23, 68, 84, 88, 120
69, 71, 73, 77, 79, 81, 85
IN
17, 18, 19, 20, 24
123, 124, 27, 33
D
99, 97, 98
22, 32, 31
ESCRIPTIONS
101, 100
116,117
115
119
121
102
103
125
126
127
128
28
34
61
63
64
89
90
91
92
95
62
58
56
57
2
Dir
T_I/O
T_I/O
T_IU
T_IU
VDD
VDD
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_O
T_I
T_I
I/O
I/O
IU
IU
IU
O
O
O
O
O
1
I
I
Name
PD[7:0]
CTL[1:0]
PHYCLK
LREQ
LINKON
LPS
D[15:0]
A[16:0]
CS#[3:0]
OE#
WE#
INT#
ID[15:0]
IA[2:0]
ICS#[1:0]
IDE_OE#
IRESET
DMARQ
DIOW#
DIOR#
IORDY
DMACK#
INTRQ
GPO1
GPO2
GPO3
GPI
RESET#
CKOUT
TEST_SEL,
TEST[1:0]
UIF
AC VDD
DC VDD
Description
Phy-Link Data Bus
Phy-Link Control Bus
49.152 MHz clock sourced by PHY
Link Request
Requests link to power up when in a low power mode
Indicates to phy that link is powered and ready
ARM external data bus
ARM external address bus
ARM external chip selects. CS0# is always used for program
ROM.
ARM external output enable. Active when reading data from
external devices including program ROM
Write Enable. Active when writing to external devices
External ARM interrupt
IDE data bus
IDE address bus
IDE chip select. Used to select the Command Block or
Control Block registers.
IDE output enable. Only used when external buffering is
required to drive IDE data bus
IDE interface reset
IDE interface write strobe
IDE interface read strobe
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
General Purpose Input
Global reset for the OXFW911. Active Low.
Clock output. 49.152 MHz clock output.
‘100’ = NORMAL OPERATION. Other settings are for
foundry test purposes only.
Leave unconnected to use internal Flash, tie low to use only
external device
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
OXFW911
Page 5

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