mn86075 Panasonic Corporation of North America, mn86075 Datasheet

no-image

mn86075

Manufacturer Part Number
mn86075
Description
Facsimile Image-processing Ic
Manufacturer
Panasonic Corporation of North America
Datasheet
LSIs for Facsimile
MN86075
Facsimile Image-Processing IC
I Overview
The MN86075 is a facsimile image-processing IC that receives the analog signal from an image sensor, which performs
a wide range of signal-processing operations on that data to create images with enhanced quality. The MN86075
reproduces high-quality images by applying 64-level halftone processing and two-dimensional MTF correction.
I Features
I Applications
Publication date: November 2001
• Image processing for high-quality image reproduction
• Implements the high processing speed of 0.5 ms/line for A3 size at 400 dpi at an image-processing clock frequency of
• Integrates offset correction, gain correction, and 8-bit A/D converter analog signal-processing circuits on the same
• Generates drive signals for all major image sensor types (CCD and CIS).
• Provides an extensive set of memory interface functions to support a wide range of applications.
• 5 V single-voltage power supply
• Image acquisition and processing for facsimile and image scanner
• Both white and black shading correction for all pixels
• Error diffusion processing to reproduce 64-level halftone images
• Two-dimensional MTF correction for text enhancement
• Multivalued smoothing removes jagged edges of slanted lines due to magnification and resolution conversion.
• Enlargement and reduction (line density conversion) without Moire patterns and with arbitrary magnification factors.
12.5 MHz.
chip.
• Standard G3 (L mode) fax (200 dpi, 1.5 ms/line)
• High-speed G3 (M mode) fax (200 dpi, 0.6 ms/line)
• High-resolution G3 (M mode) fax (400 dpi, 1.2 ms/line)
• Ultrahigh-speed G4 (H mode) fax (400 dpi, 0.5 ms/line)
Arbitrary gamma curves can be set up.
B4 or A3 size document image acquisition: SRAM (64k-bit) × 4 + FIFO (5k × 8-bit) × 1
B4 size document image acquisition: 64K SRAM (64k-bit) × 1
A3 size document image acquisition: pseudo SRAM (256k-bit) × 1
B4 or A3 size document image acquisition: SRAM (64k-bit) × 2
B4 size document image acquisition: SRAM (64k-bit) × 2
A3 size document image acquisition: SRAM (64k-bit) × 2 + SRAM (16k-bit) × 2 or SRAM (256k-bit) × 2
SDE00009BEM
1

Related parts for mn86075

mn86075 Summary of contents

Page 1

... Facsimile Image-Processing IC I Overview The MN86075 is a facsimile image-processing IC that receives the analog signal from an image sensor, which performs a wide range of signal-processing operations on that data to create images with enhanced quality. The MN86075 reproduces high-quality images by applying 64-level halftone processing and two-dimensional MTF correction. ...

Page 2

... MN86075 I Pin Arrangement (H mode) HMSWR 97 NHFWE 98 NHRSTR 99 NHRSTW 100 HRCK 101 HMWE 102 HMCWR 103 HMBWR 104 HWCK 105 HMID7 106 HMID6 107 HMID5 108 HMID4 109 HMID3 110 HMID2 111 HMID1 112 HMID0 113 MCD6 114 MCD5 115 MCD4 116 ...

Page 3

... Recommended image signal frequency (f Master clock frequency ( MCLKI T Mode (Test data input mode) Inputs data used to test the internal IC functions. Master clock frequency ( MCLKI SDE00009BEM MN86075 Function Clock mode × mode Slave f CKVD × mode Slave f CKVD × ...

Page 4

... MN86075 I Pin Descriptions (continued) 1. Mode description (3 pins) (continued) Pin Name I/O Pin No. MCM0 I 86 MCM1 I 85 (continued) 2. System interface pins (15 pins) Pin Name I/O Pin No I CPU data bus I NCS I 63 NWR(DS NRD(R/ C80 to C68 I 66 NRESET ...

Page 5

... Line 1 start timing pulse SYSL MAST (TIM2 REG) Low SYNC input * High 1 SYNC output * : Don't care NMCLKI NSYNC(O) NSYNC(I) Internal master clock output Outputs the internal master clock (the NMCLKI pin input). SYSL MAST (TIM2 REG) High 0 MCLK output SDE00009BEM MN86075 5 ...

Page 6

... MN86075 I Pin Descriptions (continued) 4. Sensor Interface Pins (6 pins) Pin Name I/O Pin No. FCK1 O 83 SCLK O FCK2 O 82 NSCLK O FSG NSTPL O FR1 O 81 FR2 O 80 SENTIM Note) : Don't care 6 CCD : 1 (TIM1 REG) Reduced CCD sensor φ1 clock: CKVD1/2 CCD : 0 (TIM1 REG) ...

Page 7

... Serial mode IPARA: 0 (IBCNT REG) Video enable Low: Image data valid period High: Image data invalid period Parallel data acknowledge input Data send acknowledge signal for DREQ Low: Data send acknowledge enable High: Data send acknowledge disable SDE00009BEM MN86075 Function Function 7 ...

Page 8

... MN86075 I Pin Descriptions (continued) 6. Image Bus Interface Pins (5 pins) (continued) Pin Name I/O Pin No. VSCK O 50 NVSCK O VSDA O 51 NVSDA O 7. Parallel I/O Pins (8 pins) Pin Name I/O Pin No. VADD7 I 52 NHROCS O VPD7 O/Hi-Z VSCD7 O CKVG O SBUS7 O Note Don't care 8 Parallel mode IPARA: 1 (IBCNT REG) ...

Page 9

... Black shading correction data input and output HKWR: low: Input HKWR: high: Output PSD2 : 1, PSD1 : 0, PSD0 : 0 (IBCNT REG) Two-valued parallel image signal output (parallel interface) NDACK: low: Output mode NDACK: high: High impedance PSD2 : 1, PSD1 : 0, PSD0 : 1 (IBCNT REG) Shading correction image signal output SDE00009BEM MN86075 9 ...

Page 10

... MN86075 I Pin Descriptions (continued) 7. Parallel I/O Pins (8 pins) (continued) Pin Name I/O Pin No. VGSD4 PSD2 : 1, PSD1 : 0, PSD0 : 0 (IBCNT REG) VGSD0 (continued) SBUS4 to O SBUS0 Note) (1) VPD0 to VPD7 1: Black - Data direction: MSB first 0: White (2) VGSD0 to VGSD7 FF: White to 00: Black (3) VGSD0 to VGSD6 7F: White to 00: Black ...

Page 11

... White shading ROM OE control EEROM WE control EEROM address high-order bits (LMA0:9 are used for the low-order bits of the address.) Output port A (8 bits) Output port B (8 bits) SDE00009BEM MN86075 Other items Image signal frequencies Maximum: 12.5 MHz † EXSCD 0: Internal SCD processing ...

Page 12

... MN86075 I Pin Descriptions (continued) 8.2. M Mode Pin Name I/O Pin No. MMED0 to I MMED7 11 MMFD0 to I/O 127 to MMFD6 121 MMFD7 10 MMLD0 to I/O 120 to MMLD6 114 MSID0 to I 113 to MSID7 106 MMA0 MMA7 88 MMA8 97 MMA9 96 MMA10 to 104 to MMA12 102 MMA13 6 MSA0 O 2 MSA1 105 NMMEWE ...

Page 13

... Gain control circuit 1 - Gain increasing resistor connection Gain control circuit 1 - Gain reducing resistor connection Gain control circuit 1 - Initialization control Gain control circuit 2 - Output Gain control circuit 2 - Gain increasing resistor connection Gain control circuit 2 - Gain reducing resistor connection Gain control circuit 2 - Initialization control SDE00009BEM MN86075 Function Function 13 ...

Page 14

... MN86075 I Pin Descriptions (continued) 9. Analog Pins (20 pins) (continued) Pin Name I/O Pin No. OFHC1 O 20 OFHC2 O 22 OFOUT1 O 19 OFOUT2 Electrical Characteristics 1. Absolute Maximum Ratings at V Parameter Supply voltage Input voltage Output voltage Input/output voltage Analog voltage Power dissipation Operating temperature Storage temperature Note) 1. † ...

Page 15

... DD In the high-impedance state V IH6 V IL6 = −2 OH6 OH5 = 2 OL6 OL5 = LK6 the high-impedance state SDE00009BEM MN86075 = 0°C to 70°C a Min Typ Max  50 100 0.8 × V   V 0.8 SS   ±10 0.7 × V   ...

Page 16

... MN86075 I Electrical Characteristics (continued Characteristics 0°C to 70° Parameter 1) Clock timing H mode NMCLK cycle time H mode NMCLK high-level pulse width H mode NMCLK low-level pulse width M mode NMCLK cycle time M mode NMCLK high-level pulse width M mode NMCLK low-level pulse width ...

Page 17

... MXIS t MXIH t OEMD = 15 ns ACC t t MCEWH1 t MCWD1 t LMWED1 t MWEWL1 MXOH1 = 15 ns ACC t MCEWH2 t MCEWL2 t MCWD2 for the NMCLKI pin. DD SDE00009BEM MN86075 = 0.7 × 0.2 × Min Typ Max   20   10   50   10   50   20  ...

Page 18

... MN86075 I Electrical Characteristics (continued Characteristics 0°C to 70°C (continued Parameter (L mode, MAG : 0, STK : 0, RSH : (continued) Pseudo SRAM : T NLMWE low-level pulse width NLMWE rising edge to LMXD output hold time t (L mode, MAG : 1, STK : 0, RSH : NLMCE high-level pulse width ...

Page 19

... MWEWL6 t LMOH6 MXOH6 = 30 ns ACC t CKVM t MMA t MXISM t MXIHM t MAWE t MWED MMOED t MLWEW MXOHM t OEMDM for the NMCLKI pin. DD SDE00009BEM MN86075 = 0.7 × 0.2 × Min Typ Max   MCYC −5 −10   t MCYC   10   10  ...

Page 20

... MN86075 I Electrical Characteristics (continued Characteristics 0°C to 70°C (continued Parameter (H mode) (maximum 12.5 MHz, MCLK = 25 MHz) SRAM : T MCLK to MACK output delay time MCLK to NHRSTA output delay time MCLK to HMWE output delay time MCLK rising edge to HMSD0-HMSD7 input setup time ...

Page 21

... MGL t MGH t GLW t GHW t GSD t MF1L t MF1H t MF2L t MF2H t MR1H t MR1L t MR2H for the NMCLKI pin. DD SDE00009BEM MN86075 = 0.7 × 0.2 × Min Typ Max Unit   ±8   ±8   ±8   10   0   ...

Page 22

... MN86075 I Electrical Characteristics (continued Characteristics 0°C to 70°C (continued Parameter 9) CCD sensor interface (continuted) NMCLKI rising edge to FR2 falling edge output delay time FR1 falling edge to FCK1 falling edge or FR2 rising edge output delay time FR2 falling edge to FCK1 riging edge or FR2 ...

Page 23

... R V OFD OFHC = OFHC OFHC DD OFHC = DSOUT OFHC DD OFOUT = OFOUT OFHC SS OFOUT SDE00009BEM MN86075 Min Typ Max   ±100  9.5 20.0  11.5 20   ±100 SS  1.0 3.7   ±100 Unit nA kΩ kΩ ...

Page 24

... MN86075 I Package Dimensions (Unit: mm) • LQFP128-P-1818C (Lead-free package 128 1 0.50 (1.25) Seating plane 24 20.00 ±0.20 18.00 ±0. 0.20 ±0.05 0.10 M 0.10 SDE00009BEM (1.00) 0° to 10° 0.50 ±0.20 (0.60) ...

Page 25

Request for your special attention and precautions in using the technical information and (1) If any of the products or technical information described in this book exported or provided to non-residents, the laws and regulations of the ...

Related keywords