ch5001a ETC-unknow, ch5001a Datasheet
ch5001a
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ch5001a Summary of contents
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... R Shutter O Control 288 Control RGB Gamma Matrix to Correct Multiply YCrCB Figure 1: Block Diagram CH5001A zones for backlight compensation BUS AS HREF PDP* Timing HS* & VS* Mode Color CLKOUT Control Reset* XI/Fin ...
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... Figure 2: 52 Contact Ceramic LCC (Top View 1mm 43 42 Image Array .600 in Sq CH5001A AVDD ARF ARF2 AGND CRF VREF AVDD XI/FIN XO AGND DGND PDP* DVDD 201-0000-032 Rev 3.0, 6/2/99 ...
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... CHRONTEL 1301 um Package Centerline Figure 3: CH5001 Array Image Offset 201-0000-032 Rev 3.0, 6/2/ Image Array CMOS Die Package Centerline 4906.7 um CH5001A 3670 ...
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... Crystal Output A 27 MHz (± 50 ppm, parallel resonance) crystal may be attached between XO and XI/FIN. Crystal Input or External input A 27 MHz (± 50 ppm, parallel resonance) crystal should be attached between XO and XI/FIN. An external CMOS compatible clock can be connected to XI/FIN as an alternative. CH5001A 201-0000-032 Rev 3.0, 6/2/99 ...
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... A 0.1 F decoupling capacitor should be connected between CMB2 and AGND. Power Up Detect (internal pull-up) These pins are shared with the C[6:0] chrominance output function. At power-up they are inputs controlling the default value of IIC register bits M0, ADDO, PD, ASW[3:0]. Attach 100K Ohms to DGND to pull low. NOTE: PUD[5:0]* are logically inverted CH5001A 5 ...
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... DAC. When the ASBE bit is a one (default) this DAC value is determined automatically, via a feedback loop which monitors the A/D output signal. When the ASBE bit is a zero, the DAC can be con- trolled via BCLMP[7:0 GaindB Gain n CH5001A 201-0000-032 Rev 3.0, 6/2/99 ...
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... Format the data stream for the desired type of output: In addition to the selection of CCIR601 or the different CIF and QCIF modes, the output format can be selected between 16-bit data (8-bit Y and 8-bit time multiplexed CrCb), and 8-bit data (time multiplexed Cb,Y,Cr,Y data at twice the rate). 201-0000-032 Rev 3.0, 6/2/99 CH5001A 7 ...
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... Auto shutter speed — The auto-shutter loop speed can be controlled via ASSPD[2:0]. Bus control: The CH5001 is controlled via a 2 pin serial interface. The description of this interface, and all registers accessible via the interface is described later in the data sheet. 8 CH5001A 201-0000-032 Rev 3.0, 6/2/99 ...
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... The Mode[0] bit can be used to select between NTSC or PAL output at power up. No pull-down resistor - PAL operation Pull-down resistor - NTSC operation ASW[3:0] The auto-shutter window can be selected at power up. See the register description for corresponding window selection. Logically inverted inputs No pull-down resistors gives window "0", Center location CH5001A 9 ...
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... The CH5001 due to the specified minimum sink current of 3mA at P – 0. and C, the total capacitance pF) P CH5001A +VDD R P DATAN2 OUT SCLK DATA IN2 IN2 SLAVE ) input 201-0000-032 Rev 3.0, 6/2/99 ...
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... HIGH level, this input current limits the maximum value (where and I DD input ACK Data ACK 1 CH5001 CH5001 acknowledge acknowledge CH5001A Transfer Protocol input Stop Data n ACK CH5001 Condition acknowledge AS ...
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... Register Address Byte (RAB) is the data to be written into the register specified by AR[5:0]. If autoInc = 0, then another RAB is expected from the master device followed by another data byte, and so on AR[4] AR[3] SC from 1 2 Master Start Condition Figure 6: Acknowledge on the Bus CH5001A AR[2] AR[1] AR[0] not acknowledge acknowledge 8 9 clock pulse for acknowledgment 201-0000-032 Rev 3.0, 6/2/99 ...
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... CH5001 acknowledge acknowledge RAB ACK Data ACK Figure 7: Alternating Write Cycles CH5001 acknowledge RAB n ACK Data n CH5001A CH5001 CH5001 acknowledge acknowledge RAB ACK Data ACK Condition CH5001 CH5001 acknowledge acknowledge ACK ...
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... Condition Figure 9: Alternating Read Cycle CH5001 CH5001 acknowledge ACK Restart Device R/W* Condition Figure 10 shows an auto-increment read cycle terminated by a STOP or CH5001A CH5001 acknowledge Master does not acknowledge R/W* ACK Data 1 ACK Restart Condition ...
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... Color Space Converter matrix coefficient for 1000 row 3, column 4. 12 xxx0 Black balance offset for Red channel. . 0000 13 xxx0 Black balance offset for Green channel. 0000 14 xxx0 Black balance offset for Blue channel. 0000 CH5001A Description 15 ...
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... Determines Master clock frequency, CLKOUT 1001 control, and A/D Direct Output mode 23 0011 Determines internal clock delay and A/D full 1001 scale value 24 xxx1 4: ResetB provides software reset 0000 3-0: Reserved. 26 0000 Holds the address of the IIC register being 0000 accessed CH5001A Description 201-0000-032 Rev 3.0, 6/2/99 ...
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... ASCSC ASWD ASW3 ASBC2 ASBC1 ASBC0 ASWC5 ASWC4 ASWC3 ESLE4 ESLE3 Reserved Reserved ADDO Reserved Reserved CLKDLY3 ResetB Reserved AR5 AR4 AR3 CH5001A FR2 FR1 FR0 HS2 HS1 HS0 VS2 VS1 VS0 ESLH2 ESLH1 ESLH0 ESLL2 ESLL1 ESLL0 ...
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... Cb0 Cr0 Cb2 Cb0 Cr0 Cb2 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cb0 Y0 Cr0 Y1 Cb2 Y2 CH5001A Symbol: MOF Address: 00h Bits R/W R PUD6 128 128 Y3 Y4 Cr2 Cb4 128 Y3 128 ...
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... Cb0 Y0 Y0 Cr0 Cr0 128 128 16 16 128 128 Y0i Y1 Y1i Y2 Y2i Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 CH5001A 128 128 16 16 128 128 Y2 Y4 Cr0 Cb4 16 16 128 128 128 128 ...
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... Lines Pixels Lines /Line /Line 352 288 176 144 176 144 88 72 704 240 352 240 704 288 352 288 352 288 176 144 176 144 88 72 CH5001A ...
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... CH5001A Symbol:FR Address:01h Bits FR2 FR1 FR0 R/W R/W R Frame Max Shutter Max Rate Length Shutter (register (Hz) ...
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... HS5 HS4 HS3 R/W R/W R Border Active (CLKOUT) (CLKOUT) 122 8 704 132 8 704 CH5001A Frame Max Shutter Rate Length (Hz) (register value) 30 99,957 24 124,839 20 149,935 15 199,914 12 249,892 8 374,946 4 749,892 1 2,097,151 24 124,704 20 149,472 15 199,296 ...
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... IIC register content. 201-0000-032 Rev 3.0, 6/2/ VS4 VS3 R/W R ESLH5 ESLH4 ESLH3 R/W R/W R ESLL5 ESLL4 ESLL3 R/W R/W R CH5001A Symbol:VS Address:03h Bits VS2 VS1 VS0 R/W R/W R Symbol:ESLH Address:04h Bits ESLH2 ESLH1 ESLH0 R/W R/W R Symbol:ESLL Address:05h Bits:8 2 ...
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... ROS4 ROS3 R/W R CH5001A Symbol:CSC11-CSC34 Address:06h-11h Bits:8 each 2 1 CSC##2 CSC##1 CSC##0 R/W R/W R/W Binary Symbol:ROS Address:12h Bits ROS2 ROS1 ROS0 R/W R/W ...
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... GOS4 GOS3 R/W R BOS4 BOS3 R/W R CRG5 CRG4 CRG3 R/W R/W R CBG5 CBG4 CBG3 R/W R/W R CH5001A Symbol:GOS Address:13h Bits GOS2 GOS1 GOS0 R/W R/W R Symbolist Address:14h Bits BOS2 BOS1 BOS0 R/W R/W R Symbol:CRG Address:15h Bits CRG2 CRG1 ...
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... GAM1 GAM0 Reserved R/W R/W R Gamma 1.0 1.6 2.2 2 BCLMP5 BCLMP4 BCLMP3 R/W R/W R Reserved PD VSP R/W R/W R/W 0 PUD4* 0 CH5001A Symbol: PSHG Address:17h Bits PSHG2 PSHG1 PSHG0 R/W R/W R Symbol:BCLMP Address:18h Bits BCLMP2 BCLMP1 BCLMP0 R/W R/W R Symbol:MISC Address:19h Bits HSP BDR1 BDR0 ...
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... DID5 DID4 DID3 Test IOC1 IOC0 R/W R/W R TM5 TM4 TM3 CH5001A Symbol:DID Address:1Ah Bits DID2 DID1 DID0 Symbol:TST Address:1Bh Bits CSH2 CSH1 CSH0 R/W R/W R Symbol:TM Address:1Ch ...
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... Figure 11: ASW Register Possible Windows ASGE Reserved Reserved R/W R/W R ASCSC ASWD ASW3 R/W R/W R PUD3 CH5001A Address:1Dh Bits ASSPD2 ASSPD1 ASSPD0 R/W R/W R Symbol:ASW Address:1Eh Bits ASW2 ASW1 ASW0 R/W R/W R/W PUD2* PUD1* PUD0 201-0000-032 Rev 3.0, 6/2/99 ...
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... A/D output MAX (A/D, Y[7:0 ASBC2 ASBC1 ASBC0 R/W R/W R ASWC5 ASWC4 ASWC3 R/W R/W R ESLE4 ESLE3 R/W R/W 0 CH5001A Symbol:ASBC Address:1Fh Bits ASBT2 ASBT1 ASBT0 R/W R Symbol:ASWC Address:20h Bits ASWC2 ASWC1 ASWC0 R/W R Symbol: ESLE Address:21h Bits:5 ...
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... A/D full scale range volt this location sets the A/D full scale range at + 0.25 volt. This bit can be combined with the PSHG[2:0] to form a 4-bit control Reserved Reserved ADDO R/W R/W R PUD5 Reserved Reserved CKDLY3 R/W R/W R CH5001A Symbol:MISC2 Address:22h Bits CLKOUTP DVC MCF R/W R/W R Symbol:MISC3 Address:23h Bits CKDLY2 CKDLY1 CKDLY0 R/W R/W ...
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... Ambient operating temperature A 201-0000-032 Rev 3.0, 6/2/ ResetB Reserved R/W R AR5 AR4 AR3 Min - 0.5 1 GND - 0 Min 4.75 5.00 4.75 5. CH5001A Symbol:PD Address:24h Bits Reserved Reserved Reserved R/W R/W R Symbol:AR Address:26h Bits AR2 AR1 AR0 Typ Max Units 7.0 V Vdd + 0 ...
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... Figure 12: Timing Diagram (M[2: Start = 0) Note: The output pixel Cb0 will be delayed by 2 times the value of the HStart register CLKOUT cycles, if HStart is non-zero. 32 Test Condition @TA Ioh =.400 mA Iol = 3.2 mA Description t VSW Cr0 CH5001A Min Typ Max 2.8 0.4 3 GND 0.8 -10 10 Min Typ Max 2 ...
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... Line) C (Odd Cb0 Line) CRS Figure 14: Timing Diagram (M[2: Note: See the HStart register description for the relationship between HS* and the first active data (Cb0) 201-0000-032 Rev 3.0, 6/2/99 t VSW Y0 Cr0 t VSW Y2 Y1 80h 80h Cr0 Cb2 CH5001A Y0i Cb1 Y3 80h Cr2 33 ...
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... Cr0 Y1 Cb2 ORDERING INFORMATION Package type Number of pins LCC 52 Chrontel 2210 O’Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Tax: (408) 383-9338 www.chrontel.com Email: sales@chrontel.com CH5001A Line Line Line Line Line Blank 286 287 288 1 Y2 Blank Blank Blank Voltage supply 5V 201-0000-032 Rev 3 ...