ch5001a ETC-unknow, ch5001a Datasheet - Page 12

• Manufacturer Part Number: ch5001a
• Description: Cmos Color Digital Video Camera
• Manufacturer: ETC-unknow

CHRONTEL
AR[5:0]
The following two sections describe the operation of the serial interface for the four combinations of R/W* = 0,1
and AutoInc = 0,1.
CH5001 Write Cycle Protocols (R/W* = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the
mastertransmitter. The mastertransmitter releases the SD line (HIGH) during the acknowledge clock pulse. The
slave-receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW
during the HIGH period of the clock pulse. The CH5001 always acknowledges for writes (see Figure 6). Note that
the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver
.
Figure 7 shows two consecutive alternating write cycles for AutoInc = 0 and R/W* = 0. The byte of information
following the Register Address Byte (RAB) is the data to be written into the register specified by AR[5:0]. If
autoInc = 0, then another RAB is expected from the master device followed by another data byte, and so on.
12
Table 4. Register Address Byte (RAB)
B7
X
AutoInc
B6
Write: After writing data into a register, the address register will automatically be incremented
Read: Before loading data from a register to the on-chip temporary register (getting ready to
0:
Write: After writing data into a register, the address register will remain unchanged until a new
Read: Before loading data from a register to the on-chip temporary register (getting ready to
Specifies the Address of the Register to be Accessed .
This register address is loaded into the address register of the CH5001. The R/W* access, which
follows, is directed to the register specified by the content stored in the address register.
By Master-Transmitter
by one.
be serially read), the address register will automatically be incremented by one.
However, for the first read after an RAB, the address register will not be changed.
Auto-increment disabled (alternating mode).
RAB is written.
be serially read), the address register will remain unchanged.
SD Data Output
SD Data Output
By the CH5001
AR[5]
B5
Figure 6: Acknowledge on the Bus
SC from
Master
Condition
AR[4]
Start
B4
1
AR[3]
B3
2
not acknowledge
acknowledge
AR[2]
B2
acknowledgment
8
clock pulse for
201-0000-032 Rev 3.0, 6/2/99
AR[1]
B1
9
CH5001A
AR[0]
B0