ch5001a ETC-unknow, ch5001a Datasheet - Page 11

• Manufacturer Part Number: ch5001a
• Description: Cmos Color Digital Video Camera
• Manufacturer: ETC-unknow

CHRONTEL
Due to the desired noise margin of 0.2V
The R
Both read and write cycles can be executed in Alternating and Auto-increment modes. Alternating mode expects a
register address prior to each read or write from that location (i.e., transfers alternate between address and data).
Auto-increment mode allows you to establish the initial register location, then automatically increments the register
address after each subsequent data access (i.e., transfers will be address, data, data, data...). A basic serial port
transfer protocol is shown in Figure 5 and described below.
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
3. Upon receiving the first START condition, the CH5001 expects a Device Address Byte (DAB) from the
4. After the DAB is received, the CH5001 expects a Register Address Byte (RAB) from the master. The
R/W
201-0000-032 Rev 3.0, 6/2/99
Table 3. Device Address Byte (DAB)
START condition. Transitions of address and data bits can only occur while SC is low.
STOP condition.
master device. The value of the device address is shown in the DAB data format below. Note that B[2:1] is
determined by the state of the AS pin (see Table 1 for details).
format of the RAB is shown in the RAB data format below (note that B7 is not used).
SD
SC
B7
P
1
limit depends on V
Condition
Start
B6
0
R
Read/Write Indicator
0:
1:
Device ID
P
1 - 7
>= (100 x V
DD
Master device will write to the CH5001 at the register location specified by the address
AR[5:0]
Master device will read from the CH5001 at the register location specified by the
address AR[5:0]. AutoInc Register Address Auto-Increment - to facilitate sequential
R/W of registers 1: Auto-Increment enabled (auto-increment mode).
and is shown below:
R/W*
Figure 5: Serial Port Transfer Protocol
B5
8
0
DD
acknowledge
)/ I
DD
CH5001
ACK
9
input
for the HIGH level, this input current limits the maximum value of R
(where: R
B4
0
Data
1 - 8
1
P
is in k and I
acknowledge
ACK
CH5001
B3
9
1
input
Data n
AS*
B2
1 - 8
is in A) Transfer Protocol
acknowledge
CH5001
ACK
9
B1
AS
CH5001A
Condition
R/W
B0
Stop
11
P
.