SN74LS196 MOTOROLA [Motorola, Inc], SN74LS196 Datasheet - Page 3

• Manufacturer Part Number: SN74LS196
• Description: 4-STAGE PRESETTABLE RIPPLE COUNTERS
• Manufacturer: MOTOROLA [Motorola, Inc]

FUNCTIONAL DESCRIPTION
cade and binary ripple counters. The LS196 Decade Counter
is partitioned into divide-by-two and divide-by-five sections
while the LS197 is partitioned into divide-by-two and divide-
by-eight sections, with all sections having a separate Clock in-
put. In the counting modes, state changes are initiated by the
HIGH to LOW transition of the clock signals. State changes of
the Q outputs, however, do not occur simultaneously because
of the internal ripple delays. When using external logic to de-
code the Q outputs, designers should bear in mind that the un-
equal delays can lead to decoding spikes and thus a decoded
signal should not be used as a clock or strobe. The CP 0 input
serves the Q 0 flip-flop in both circuit types while the CP 1 input
serves the divide-by-five or divide-by-eight section. The Q 0
output is designed and specified to drive the rated fan-out plus
the CP 1 input. With the input frequency connected to CP 0 and
Q 0 driving CP 1 , the LS197 forms a straightforward module-16
counter, with Q 0 the least significant output and Q 3 the most
NOTES:
1. Signal applied to CP 0 , Q 0 connected to CP 1 .
2. Signal applied to CP 1 , Q 3 connected to CP 0 .
The LS196 and LS197 are asynchronously presettable de-
COUNT
0
1
2
3
4
5
6
7
8
9
Q 3
H
H
L
L
L
L
L
L
L
L
DECADE (NOTE 1)
Q 2
H
H
H
H
L
L
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition
MR
SN54/74LS196 SN54/74LS197
H
H
L
Q 1
H
H
H
H
L
L
L
L
L
L
Figure 2. LS196 COUNT SEQUENCES
INPUTS
FAST AND LS TTL DATA
PL
H
X
L
MODE SELECT TABLE
Q 0
H
H
H
H
H
L
L
L
L
L
5-3
COUNT
CP
X
X
0
1
2
3
4
5
6
7
8
9
significant output.
ate in two different count sequences, as indicated in the tables
of Figure 2. With the input frequency connected to CP 0 and
with Q 0 driving CP 1 , the circuit counts in the BCD (8, 4, 2, 1)
sequence. With the input frequency connected to CP 1 and Q 3
driving CP 0 , Q 0 becomes the low frequency output and has a
50% duty cycle waveform. Note that the maximum counting
rate is reduced in the latter (bi-quinary) configuration because
of the interstage gating delay within the divide-by-five section.
Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously
presettable. A LOW on the Parallel Load input (PL) overrides
the clock inputs and loads the data from Parallel Data (P 0 – P 3 )
inputs into the flip-flops. While PL is LOW, the counters act as
transparent latches and any change in the P n inputs will be re-
flected in the outputs.
The LS196 Decade Counter can be connected up to oper-
The LS196 and LS197 have an asynchronous active LOW
Reset (Clear)
Parallel Load
RESPONSE
RESPONSE
Q 0
H
H
H
H
H
L
L
L
L
L
Count
BI-QUINARY (NOTE 2)
Q 3
H
H
L
L
L
L
L
L
L
L
Q 2
H
H
H
H
L
L
L
L
L
L
Q 1
H
H
H
H
L
L
L
L
L
L