LTC1409 LINER [Linear Technology], LTC1409 Datasheet - Page 8

• Manufacturer Part Number: LTC1409
• Description: 12-Bit, 800ksps Sampling A/D Converter with Shutdown
• Manufacturer: LINER [Linear Technology]

APPLICATIONS
LTC1409
CONVERSION DETAILS
The LTC1409 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the +A
connected to the sample-and-hold capacitors (C
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 150ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
8
+A
–A
IN
IN
+V
Figure 1. Simplified Block Diagram
DAC
–V
HOLD
HOLD
DAC
U
+C
–C
–C
+C
SAMPLE
SAMPLE
DAC
DAC
INFORMATION
U
SAR
SAMPLE
ZEROING SWITCHES
12
+
–
W
IN
capacitors to ground,
HOLD
HOLD
COMP
and –A
LATCHES
OUTPUT
IN
LTC1409 • F01
U
inputs are
SAMPLE
•
•
•
D11
D0
)
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DACs output balances the +A
charges. The SAR contents (a 12-bit data word) which
represents the difference of +A
the 12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1409 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. Figure 2 shows typical
LTC1409 plots.
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
–100
–120
–100
–120
–20
–40
–60
–80
–20
–40
–60
–80
0
0
0
0
f
f
SFDR = 89dB
SINAD = 72.5dB
SAMPLE
IN
50
= 375kHz
50
100
100
= 800kHz
FREQUENCY (kHz)
FREQUENCY (kHz)
150
150
200
200
IN
f
f
SFDR = 89.1dB
SINAD = 73.1dB
SAMPLE
IN
250
250
and –A
= 97.45kHz
300
300
= 800kHz
LT1409 • F02a
LT1409 • F02b
350
350
IN
IN
are loaded into
and –A
400
400
IN
input