LTC2259-16 LINER [Linear Technology], LTC2259-16 Datasheet - Page 16

• Manufacturer Part Number: LTC2259-16
• Description: 16-Bit, 80Msps Ultralow Power 1.8V ADC
• Manufacturer: LINER [Linear Technology]

LTC2259-16
16
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above V
is from 1.1V to 1.6V. In the differential encode mode,
ENC
falsely triggering the single-ended encode mode. For good
jitter performance ENC
and fall times.
–
should stay at least 200mV above ground to avoid
ENC
ENC
DD
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
1.8V TO 3.3V
+
–
(up to 3.6V), and the common mode range
LTC2259-16
0V
15k
30k
V
DD
+
ENC
ENC
and ENC
V
DD
+
–
LTC2259-16
30k
–
should have fast rise
CMOS LOGIC
DIFFERENTIAL
COMPARATOR
BUFFER
225916 F11
225916 F10
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC
to ground and ENC
input. ENC
to 3.3V CMOS logic levels can be used. The ENC
is 0.9V. For good jitter performance ENC
rise and fall times.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
25Ω
D1
+
Figure 13. PECL or LVDS Encode Drive
can be taken above V
Figure 12. Sinusoidal Encode Drive
PECL OR
CLOCK
LVDS
0.1μF
+
is driven with a square wave encode
0.1μF
0.1μF
T1
1:4
ENC
ENC
+
–
DD
100Ω
100Ω
LTC2259-16
(up to 3.6V) so 1.8V
225916 F13
+
0.1μF
should have fast
–
ENC
ENC
is connected
+
–
+
threshold
LTC2259-16
225916f
225916 F12